From patchwork Wed Apr 3 20:56:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 233585 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CA9852C0101 for ; Thu, 4 Apr 2013 07:58:14 +1100 (EST) Received: from localhost ([::1]:39509 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNUl2-0004W7-TM for incoming@patchwork.ozlabs.org; Wed, 03 Apr 2013 16:58:12 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNUkN-00048q-V7 for qemu-devel@nongnu.org; Wed, 03 Apr 2013 16:57:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNUkF-0006DG-4n for qemu-devel@nongnu.org; Wed, 03 Apr 2013 16:57:31 -0400 Received: from mail-oa0-f46.google.com ([209.85.219.46]:50688) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNUkF-0006D0-0Z; Wed, 03 Apr 2013 16:57:23 -0400 Received: by mail-oa0-f46.google.com with SMTP id k1so2042546oag.33 for ; Wed, 03 Apr 2013 13:57:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer; bh=YoHRIg8IkIHBu7V4v9Z9NWYz/ZxhEIc1Uq5JNPLiFho=; b=klMaiSLpDfI+SFSQ83vpMsByM/HQc/DKjyoi42HTq4gPGX0t6Lz1UannR/JHn3sGG9 bg8hXseMJupJuKwmQEVHYvi2/5ast4v3Ii7CoT6wKiV0ihXC/vwXfVaRqMupiPzlqqTh YpcaX0U8A/Wnc7o9vOUlwO5V7JF45M0B6oTGb4blUdw6+CMvkbiv4nPML3+lxqGpYBqb HlAmWti4gAzJObAu/Nf141DVwvkOqQnOY9hLxO++MZIa3JnGhrukWbbvJ2AvJYs6GNi+ XvsvaMqKFhY5LOeYvqB31mF5n5CcWcX8oOBPYCudPzdiKsVON6rbhGswbe4nLcIpdfB/ QtSg== X-Received: by 10.60.147.165 with SMTP id tl5mr2261829oeb.61.1365022641755; Wed, 03 Apr 2013 13:57:21 -0700 (PDT) Received: from pebble.com ([12.236.175.36]) by mx.google.com with ESMTPS id qk4sm3457885obc.5.2013.04.03.13.57.19 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 03 Apr 2013 13:57:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Apr 2013 15:56:45 -0500 Message-Id: <1365022605-18942-1-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.219.46 Cc: qemu-ppc@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PATCH v2] target-ppc: Fix narrow-mode add/sub carry output X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself was fixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62. But we still need to produce the full 64-bit addition. Simplify the conditions at the top of the functions for when we need a new temporary. Only plain addition is important enough to warrent avoiding the temporary, and the extra tcg move op that would come with it. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno Tested-by: Aurelien Jarno --- Version 2 fixes the temporary creation problem spotted by Aurelien. --- target-ppc/translate.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 5e741d1..fa1778a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -768,22 +768,25 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, { TCGv t0 = ret; - if (((compute_ca && add_ca) || compute_ov) - && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) { + if (compute_ca || compute_ov) { t0 = tcg_temp_new(); } if (compute_ca) { if (NARROW_MODE(ctx)) { + /* Caution: a non-obvious corner case of the spec is that we + must produce the *entire* 64-bit addition, but produce the + carry into bit 32. */ TCGv t1 = tcg_temp_new(); - tcg_gen_ext32u_tl(t1, arg2); - tcg_gen_ext32u_tl(t0, arg1); - tcg_gen_add_tl(t0, t0, t1); - tcg_temp_free(t1); + tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ + tcg_gen_add_tl(t0, arg1, arg2); if (add_ca) { tcg_gen_add_tl(t0, t0, cpu_ca); } - tcg_gen_shri_tl(cpu_ca, t0, 32); + tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ + tcg_temp_free(t1); + tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ + tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); } else { TCGv zero = tcg_const_tl(0); if (add_ca) { @@ -1122,24 +1125,30 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, { TCGv t0 = ret; - if (compute_ov && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) { + if (compute_ca || compute_ov) { t0 = tcg_temp_new(); } if (compute_ca) { /* dest = ~arg1 + arg2 [+ ca]. */ if (NARROW_MODE(ctx)) { + /* Caution: a non-obvious corner case of the spec is that we + must produce the *entire* 64-bit addition, but produce the + carry into bit 32. */ TCGv inv1 = tcg_temp_new(); + TCGv t1 = tcg_temp_new(); tcg_gen_not_tl(inv1, arg1); - tcg_gen_ext32u_tl(t0, arg2); - tcg_gen_ext32u_tl(inv1, inv1); if (add_ca) { - tcg_gen_add_tl(t0, t0, cpu_ca); + tcg_gen_add_tl(t0, arg2, cpu_ca); } else { - tcg_gen_addi_tl(t0, t0, 1); + tcg_gen_addi_tl(t0, arg2, 1); } + tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ tcg_gen_add_tl(t0, t0, inv1); - tcg_gen_shri_tl(cpu_ca, t0, 32); + tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ + tcg_temp_free(t1); + tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ + tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); } else if (add_ca) { TCGv zero, inv1 = tcg_temp_new(); tcg_gen_not_tl(inv1, arg1);