diff mbox

[arm-devs,v1,1/1] cadence_uart: Flush queued characters on reset

Message ID 494c1e005e225c915d295ddfd75d992ad2dabc3c.1364964526.git.peter.crosthwaite@xilinx.com
State New
Headers show

Commit Message

Peter Crosthwaite April 3, 2013, 4:52 a.m. UTC 
Reset can be used to empty the rx-fifo. As the fifo full condition is
used to return false from can_receive, queued rx data should be flushed
on reset accordingly.

Cc: Wendy Liang <jliang@xilinx.com>
Cc: Jason Wu <huanyu@xilinx.com>

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reported-by: Jason Wu <huanyu@xilinx.com>
---

 hw/cadence_uart.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

Comments

Peter Maydell April 5, 2013, 4:04 p.m. UTC | #1 
On 3 April 2013 05:52, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote:
> Reset can be used to empty the rx-fifo. As the fifo full condition is
> used to return false from can_receive, queued rx data should be flushed
> on reset accordingly.
>
> Cc: Wendy Liang <jliang@xilinx.com>
> Cc: Jason Wu <huanyu@xilinx.com>
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Reported-by: Jason Wu <huanyu@xilinx.com>

Thanks, applied to arm-devs.next.

-- PMM
diff mbox

Patch

diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
index 5426f10..421ec99 100644
--- a/hw/cadence_uart.c
+++ b/hw/cadence_uart.c
@@ -157,6 +157,7 @@  static void uart_rx_reset(UartState *s)
 {
     s->rx_wpos = 0;
     s->rx_count = 0;
+    qemu_chr_accept_input(s->chr);
 
     s->r[R_SR] |= UART_SR_INTR_REMPTY;
     s->r[R_SR] &= ~UART_SR_INTR_RFUL;