From patchwork Wed Apr 3 04:32:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 233224 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 676362C0095 for ; Wed, 3 Apr 2013 15:35:17 +1100 (EST) Received: from localhost ([::1]:44534 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNFPl-0008P1-KT for incoming@patchwork.ozlabs.org; Wed, 03 Apr 2013 00:35:13 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59697) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNFPG-00083E-EH for qemu-devel@nongnu.org; Wed, 03 Apr 2013 00:34:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNFPF-0006NX-FO for qemu-devel@nongnu.org; Wed, 03 Apr 2013 00:34:42 -0400 Received: from mail-pd0-f182.google.com ([209.85.192.182]:49916) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNFPF-0006NL-8x for qemu-devel@nongnu.org; Wed, 03 Apr 2013 00:34:41 -0400 Received: by mail-pd0-f182.google.com with SMTP id 3so621027pdj.41 for ; Tue, 02 Apr 2013 21:34:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:in-reply-to:references:x-gm-message-state; bh=gAX++oK6G40QOVqfxLoWrPJTDzm0RcIiwrQPBS3Upu8=; b=cRjaUk1umetyw/JHTaB5Cp/NHT6E3wAT9qbknCTdlpvEpJQ/6MEOy0DOn5iKs/D6UJ x8vX4INkSoCxkGEYbDaO0HT60qmSC6YvSK9R60AlIuQNFC0ZQcQS0TtNBNHhVSYTur5e +iIRjYnZKXJSE+ceVD8pSkVFnr9SocvsUODCK7nBAyejf8EwkHGkvTQa5MgA6Tl+EMY2 pMkMaRc4EAKiROYe/AGNDxxhTQS2nxzQWS2lc2Pbw6JLsv5d7PomFIiv8eK8CBYt454g eCalYuVoYsBU92icENoSwDleYiOEklFbFjwzA7RK/zO8Q08nSlBIyVnhEn1Eeay2imwi momQ== X-Received: by 10.68.238.196 with SMTP id vm4mr95330pbc.217.1364963680517; Tue, 02 Apr 2013 21:34:40 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id gj2sm4314910pbc.25.2013.04.02.21.34.38 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Tue, 02 Apr 2013 21:34:39 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 3 Apr 2013 14:32:58 +1000 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <475b23a3c56ec5ee1a8652f33e0a12d0bb4ac7f6.1364962908.git.peter.crosthwaite@xilinx.com> References: <475b23a3c56ec5ee1a8652f33e0a12d0bb4ac7f6.1364962908.git.peter.crosthwaite@xilinx.com> In-Reply-To: References: X-Gm-Message-State: ALoCoQklCl/9FKOXI6YazdoOF1IVBpAUBgUAHLMcN+zDJ5+M98SOelAYX+6mOPptMsMfL9gPNlfj X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.192.182 Cc: Peter Crosthwaite Subject: [Qemu-devel] [PATCH arm-devs v1 06/15] xilinx_spips: Fix QSPI FIFO size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org QSPI has a bigger FIFO than the regular SPI controller. Differentiate between the two with correct FIFO sizes for each. Signed-off-by: Peter Crosthwaite --- hw/xilinx_spips.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c index 06c2ec5..78a3fec 100644 --- a/hw/xilinx_spips.c +++ b/hw/xilinx_spips.c @@ -106,6 +106,9 @@ #define RXFF_A 32 #define TXFF_A 32 +#define RXFF_A_Q (64 * 4) +#define TXFF_A_Q (64 * 4) + /* 16MB per linear region */ #define LQSPI_ADDRESS_BITS 24 /* Bite off 4k chunks at a time */ @@ -575,6 +578,10 @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp) s->num_txrx_bytes = 4; xilinx_spips_realize(dev, errp); + fifo8_destroy(&s->rx_fifo); + fifo8_destroy(&s->tx_fifo); + fifo8_create(&s->rx_fifo, RXFF_A_Q); + fifo8_create(&s->tx_fifo, TXFF_A_Q); memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi", (1 << LQSPI_ADDRESS_BITS) * 2); sysbus_init_mmio(sbd, &s->mmlqspi);