Patchwork xilinx_axienet: pump events as appropriate

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Submitter Peter Crosthwaite
Date April 3, 2013, 4:04 a.m.
Message ID <1364961849-29407-1-git-send-email-peter.crosthwaite@xilinx.com>
Download mbox | patch
Permalink /patch/233214/
State New
Headers show

Comments

Peter Crosthwaite - April 3, 2013, 4:04 a.m.
When the conditions blocking receiving are cleared, check for buffered rx
packets.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
 hw/xilinx_axienet.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)
Edgar Iglesias - April 3, 2013, 8:13 a.m.
On Wed, Apr 03, 2013 at 02:04:09PM +1000, Peter Crosthwaite wrote:
> When the conditions blocking receiving are cleared, check for buffered rx
> packets.
> 
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>



> ---
>  hw/xilinx_axienet.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
> index 5785290..07c4bad 100644
> --- a/hw/xilinx_axienet.c
> +++ b/hw/xilinx_axienet.c
> @@ -516,6 +516,8 @@ static void enet_write(void *opaque, hwaddr addr,
>              s->rcw[addr & 1] = value;
>              if ((addr & 1) && value & RCW1_RST) {
>                  axienet_rx_reset(s);
> +            } else {
> +                qemu_flush_queued_packets(qemu_get_queue(s->nic));
>              }
>              break;
>  
> -- 
> 1.7.0.4
>
Edgar Iglesias - April 3, 2013, 11:02 p.m.
On Wed, Apr 03, 2013 at 02:04:09PM +1000, Peter Crosthwaite wrote:
> When the conditions blocking receiving are cleared, check for buffered rx
> packets.
> 
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Appliead, thanks Peter



> ---
>  hw/xilinx_axienet.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
> index 5785290..07c4bad 100644
> --- a/hw/xilinx_axienet.c
> +++ b/hw/xilinx_axienet.c
> @@ -516,6 +516,8 @@ static void enet_write(void *opaque, hwaddr addr,
>              s->rcw[addr & 1] = value;
>              if ((addr & 1) && value & RCW1_RST) {
>                  axienet_rx_reset(s);
> +            } else {
> +                qemu_flush_queued_packets(qemu_get_queue(s->nic));
>              }
>              break;
>  
> -- 
> 1.7.0.4
>

Patch

diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index 5785290..07c4bad 100644
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -516,6 +516,8 @@  static void enet_write(void *opaque, hwaddr addr,
             s->rcw[addr & 1] = value;
             if ((addr & 1) && value & RCW1_RST) {
                 axienet_rx_reset(s);
+            } else {
+                qemu_flush_queued_packets(qemu_get_queue(s->nic));
             }
             break;