diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 119342e..f261628 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -150,7 +150,7 @@ void init_pllx(void)
 	debug("init_pllx entry\n");
 
 	/* get chip type */
-	chip_type = tegra_get_chip_type();
+	chip_type = tegra_get_soc_sku();
 	debug(" init_pllx: chip_type = %d\n", chip_type);
 
 	/* get osc freq */
@@ -303,7 +303,7 @@ void clock_enable_coresight(int enable)
 		 * Clock divider request for 204MHz would setup CSITE clock as
 		 * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
 		 */
-		chip = tegra_get_chip_type();
+		chip = tegra_get_soc_sku();
 		if (chip == TEGRA_SOC_T30 || chip == TEGRA_SOC_T114)
 			src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
 		else if (chip == TEGRA_SOC_T20 || chip == TEGRA_SOC_T25)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h
index e8e05d7..41f6f0e 100644
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h
@@ -80,5 +80,5 @@ void init_pllx(void);
 void powerup_cpu(void);
 void reset_A9_cpu(int reset);
 void start_cpu(u32 reset_vector);
-int tegra_get_chip_type(void);
+int tegra_get_soc_sku(void);
 void adjust_pllp_out_freqs(void);
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index a739fe2..13dac49 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -34,23 +34,31 @@
 #include <asm/arch-tegra/tegra.h>
 #include <asm/arch-tegra/warmboot.h>
 
-int tegra_get_chip_type(void)
+unsigned tegra_get_soc_type(void)
 {
-	struct apb_misc_gp_ctlr *gp;
-	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
-	uint tegra_sku_id, rev;
+	unsigned rev;
+	struct apb_misc_gp_ctlr *gp =
+		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
 	/*
-	 * This is undocumented, Chip ID is bits 15:8 of the register
-	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
-	 * Tegra30, and 0x35 for T114.
+	 * Chip ID is bits 15:8 of the register APB_MISC + 0x804,
+	 * and has value 0x20 for Tegra20, 0x30 for Tegra30, and
+	 * 0x35 for T114.
 	 */
-	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
 
+	return rev;
+}
+
+unsigned tegra_get_soc_sku(void)
+{
+	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
+	unsigned soc, tegra_sku_id;
+
+	soc = tegra_get_soc_type();
 	tegra_sku_id = readl(&fuse->sku_info) & 0xff;
 
-	switch (rev) {
+	switch (soc) {
 	case CHIPID_TEGRA20:
 		switch (tegra_sku_id) {
 		case SKU_ID_T20:
diff --git a/arch/arm/cpu/tegra20-common/pmu.c b/arch/arm/cpu/tegra20-common/pmu.c
index 2282953..19a88bc 100644
--- a/arch/arm/cpu/tegra20-common/pmu.c
+++ b/arch/arm/cpu/tegra20-common/pmu.c
@@ -44,7 +44,7 @@ int pmu_set_nominal(void)
 	int core, cpu, bus;
 
 	/* by default, the table has been filled with T25 settings */
-	switch (tegra_get_chip_type()) {
+	switch (tegra_get_soc_sku()) {
 	case TEGRA_SOC_T20:
 		core = VDD_CORE_NOMINAL_T20;
 		cpu = VDD_CPU_NOMINAL_T20;
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
index 5999f55..28dc782 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -59,9 +59,17 @@
 extern void _start(void);
 
 /**
- * Works out the SOC type used for clocks settings
+ * Works out the SKU-based SOC ID used for clocks settings
  *
  * @return	SOC type - see TEGRA_SOC...
  */
-int tegra_get_chip_type(void);
+unsigned tegra_get_soc_sku(void);
+
+/**
+ * Returns the pure CHIPID from the HIDREV register
+ *
+ * @return	8-bit HIDREV CHIPID, i.e. 0x20, 0x30, 0x35
+ */
+unsigned tegra_get_soc_type(void);
+
 void config_cache(void);
diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c
index 26b6ec7..de6d89b 100644
--- a/board/nvidia/common/emc.c
+++ b/board/nvidia/common/emc.c
@@ -40,7 +40,7 @@ int board_emc_init(void)
 {
 	unsigned rate;
 
-	switch (tegra_get_chip_type()) {
+	switch (tegra_get_soc_sku()) {
 	default:
 	case TEGRA_SOC_T20:
 		rate  = EMC_SDRAM_RATE_T20;
