From patchwork Tue Apr 2 07:10:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hurugalawadi, Naveen" X-Patchwork-Id: 232903 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id A91242C00FA for ; Tue, 2 Apr 2013 18:11:24 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:mime-version; q=dns; s=default; b=e+1/ItE1YXgW6qhu ppCwamjyUWWX49sgQk8WndR+R4ZPd9QMRb18fzNxWF6zCGKIDATeHCK+xljRpcCQ a7gYmRS5LSLZ4d67ZmHwmwsjbBTuxexAkjtZC5b/FNcGYxY9jKDlsrHaClDVPQSd ucAfXbQo9ElEsEzVoYfGckPi+dA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:mime-version; s=default; bh=hWgA7yDhoUOnv2nEjungMB RCg1Y=; b=VaJKQ1/zJrVbOiDYo/Mq2U3vsuiiqOQ8dhGYHAc6wtqy3LpiFjQMIj RHYyDfrb1Jl9CjZL507UzUE5V+CdZb6+qJxUx4p2hAGvCxgaJpsiMfY2FePyG6qT Sn0vchm0BoUfKfI1ypYQz/Or/ecrWgsTfr+iE4epfaykhSYjEYDnA= Received: (qmail 6427 invoked by alias); 2 Apr 2013 07:11:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6372 invoked by uid 89); 2 Apr 2013 07:11:04 -0000 X-Spam-SWARE-Status: No, score=-4.8 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, KHOP_THREADED, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL autolearn=ham version=3.3.1 Received: from va3ehsobe004.messaging.microsoft.com (HELO va3outboundpool.messaging.microsoft.com) (216.32.180.14) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 02 Apr 2013 07:10:59 +0000 Received: from mail121-va3-R.bigfish.com (10.7.14.234) by VA3EHSOBE014.bigfish.com (10.7.40.64) with Microsoft SMTP Server id 14.1.225.23; Tue, 2 Apr 2013 07:10:57 +0000 Received: from mail121-va3 (localhost [127.0.0.1]) by mail121-va3-R.bigfish.com (Postfix) with ESMTP id 15E2B1401DB; Tue, 2 Apr 2013 07:10:57 +0000 (UTC) X-Forefront-Antispam-Report: CIP:157.56.234.149; KIP:(null); UIP:(null); IPV:NLI; H:SN2PRD0710HT004.namprd07.prod.outlook.com; RD:none; EFVD:NLI X-SpamScore: -3 X-BigFish: PS-3(zz936eIc85fh148cI4015Izz1f42h1fc6h1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd25hf0ah1288h12a5h12bdh137ah1441h1504h1537h153bh15d0h162dh1631h1758h18e1h1946h19b5h19ceh1ad9h1b0ah1bceh34h1155h) Received: from mail121-va3 (localhost.localdomain [127.0.0.1]) by mail121-va3 (MessageSwitch) id 1364886654694289_23976; Tue, 2 Apr 2013 07:10:54 +0000 (UTC) Received: from VA3EHSMHS019.bigfish.com (unknown [10.7.14.231]) by mail121-va3.bigfish.com (Postfix) with ESMTP id 9BF0E10006C; Tue, 2 Apr 2013 07:10:54 +0000 (UTC) Received: from SN2PRD0710HT004.namprd07.prod.outlook.com (157.56.234.149) by VA3EHSMHS019.bigfish.com (10.7.99.29) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 2 Apr 2013 07:10:52 +0000 Received: from SN2PRD0710MB372.namprd07.prod.outlook.com ([169.254.5.12]) by SN2PRD0710HT004.namprd07.prod.outlook.com ([10.255.118.39]) with mapi id 14.16.0287.008; Tue, 2 Apr 2013 07:10:34 +0000 From: "Hurugalawadi, Naveen" To: Marcus Shawcroft CC: "gcc-patches@gcc.gnu.org" , Ian Bolton Subject: RE: [AArch64] Bitwise adds and subs instructions with shift Date: Tue, 2 Apr 2013 07:10:34 +0000 Message-ID: References: , <51548DBF.3080607@arm.com> In-Reply-To: <51548DBF.3080607@arm.com> MIME-Version: 1.0 X-OriginatorOrg: caviumnetworks.com X-Virus-Found: No Hi Marcus, Thanks for reviewing the patch and your comments. >> I'm not sure how good the coverage is from these test cases The shift instructions are not generated with the test case since multiply patterns are generated for the same. Its the same case with other add and sub instructions which supports both shift and multiply patterns.The zero extend versions were not generated even though test cases were implemented for them. Please find attached the modified patch that implements adds and subs instructions with multiply for aarch64 target. Please review the same and let me know if there should be any modifications in the patch. Build and tested on aarch64-thunder-elf (using Cavium's internal simulator). No new regressions. Thanks, Naveen gcc/ 2013-04-02 Naveen H.S * config/aarch64/aarch64.md (*adds_mul_imm_): New pattern. (*subs_mul_imm_): New pattern. gcc/testsuite/ 2013-04-02 Naveen H.S * gcc.target/aarch64/adds1.c: New. * gcc.target/aarch64/adds2.c: New. * gcc.target/aarch64/subs1.c: New. * gcc.target/aarch64/subs2.c: New. --- gcc/config/aarch64/aarch64.md 2013-03-26 12:51:12.180448029 +0530 +++ gcc/config/aarch64/aarch64.md 2013-04-02 11:26:33.008898964 +0530 @@ -1286,6 +1286,40 @@ (set_attr "mode" "SI")] ) +(define_insn "*adds_mul_imm_" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (plus:GPI (mult:GPI + (match_operand:GPI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_pwr_2_" "n")) + (match_operand:GPI 3 "register_operand" "rk")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (plus:GPI (mult:GPI (match_dup 1) (match_dup 2)) + (match_dup 3)))] + "" + "adds\\t%0, %3, %1, lsl %p2" + [(set_attr "v8type" "alus_shift") + (set_attr "mode" "")] +) + +(define_insn "*subs_mul_imm_" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (minus:GPI (match_operand:GPI 1 "register_operand" "rk") + (mult:GPI + (match_operand:GPI 2 "register_operand" "r") + (match_operand:QI 3 "aarch64_pwr_2_" "n"))) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (minus:GPI (match_dup 1) + (mult:GPI (match_dup 2) (match_dup 3))))] + "" + "subs\\t%0, %1, %2, lsl %p3" + [(set_attr "v8type" "alus_shift") + (set_attr "mode" "")] +) + (define_insn "*add3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ --- gcc/testsuite/gcc.target/aarch64/adds1.c 1970-01-01 05:30:00.000000000 +0530 +++ gcc/testsuite/gcc.target/aarch64/adds1.c 2013-04-01 13:40:48.189390503 +0530 @@ -0,0 +1,149 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps" } */ + +extern void abort (void); + +int +adds_si_test1 (int a, int b, int c) +{ + int d = a + b; + + /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +int +adds_si_test2 (int a, int b, int c) +{ + int d = a + 0xff; + + /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, 255" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +int +adds_si_test3 (int a, int b, int c) +{ + int d = a + (b << 3); + + /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +typedef long long s64; + +s64 +adds_di_test1 (s64 a, s64 b, s64 c) +{ + s64 d = a + b; + + /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +s64 +adds_di_test2 (s64 a, s64 b, s64 c) +{ + s64 d = a + 0xff; + + /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, 255" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +s64 +adds_di_test3 (s64 a, s64 b, s64 c) +{ + s64 d = a + (b << 3); + + /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +int main () +{ + int x; + s64 y; + + x = adds_si_test1 (29, 4, 5); + if (x != 42) + abort (); + + x = adds_si_test1 (5, 2, 20); + if (x != 29) + abort (); + + x = adds_si_test2 (29, 4, 5); + if (x != 293) + abort (); + + x = adds_si_test2 (1024, 2, 20); + if (x != 1301) + abort (); + + x = adds_si_test3 (35, 4, 5); + if (x != 76) + abort (); + + x = adds_si_test3 (5, 2, 20); + if (x != 43) + abort (); + + y = adds_di_test1 (0x130000029ll, + 0x320000004ll, + 0x505050505ll); + + if (y != 0xc75050536) + abort (); + + y = adds_di_test1 (0x5000500050005ll, + 0x2111211121112ll, + 0x0000000002020ll); + if (y != 0x9222922294249) + abort (); + + y = adds_di_test2 (0x130000029ll, + 0x320000004ll, + 0x505050505ll); + if (y != 0x955050631) + abort (); + + y = adds_di_test2 (0x130002900ll, + 0x320000004ll, + 0x505050505ll); + if (y != 0x955052f08) + abort (); + + y = adds_di_test3 (0x130000029ll, + 0x064000008ll, + 0x505050505ll); + if (y != 0x9b9050576) + abort (); + + y = adds_di_test3 (0x130002900ll, + 0x088000008ll, + 0x505050505ll); + if (y != 0xafd052e4d) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ --- gcc/testsuite/gcc.target/aarch64/adds2.c 1970-01-01 05:30:00.000000000 +0530 +++ gcc/testsuite/gcc.target/aarch64/adds2.c 2013-04-01 13:40:48.189390503 +0530 @@ -0,0 +1,155 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps" } */ + +extern void abort (void); + +int +adds_si_test1 (int a, int b, int c) +{ + int d = a + b; + + /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ + /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +int +adds_si_test2 (int a, int b, int c) +{ + int d = a + 0xfff; + + /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, 4095" } } */ + /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, 4095" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +int +adds_si_test3 (int a, int b, int c) +{ + int d = a + (b << 3); + + /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ + /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +typedef long long s64; + +s64 +adds_di_test1 (s64 a, s64 b, s64 c) +{ + s64 d = a + b; + + /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ + /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +s64 +adds_di_test2 (s64 a, s64 b, s64 c) +{ + s64 d = a + 0x1000ll; + + /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, 4096" } } */ + /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, 4096" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +s64 +adds_di_test3 (s64 a, s64 b, s64 c) +{ + s64 d = a + (b << 3); + + /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ + /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +int main () +{ + int x; + s64 y; + + x = adds_si_test1 (29, 4, 5); + if (x != 42) + abort (); + + x = adds_si_test1 (5, 2, 20); + if (x != 29) + abort (); + + x = adds_si_test2 (29, 4, 5); + if (x != 4133) + abort (); + + x = adds_si_test2 (1024, 2, 20); + if (x != 5141) + abort (); + + x = adds_si_test3 (35, 4, 5); + if (x != 76) + abort (); + + x = adds_si_test3 (5, 2, 20); + if (x != 43) + abort (); + + y = adds_di_test1 (0x130000029ll, + 0x320000004ll, + 0x505050505ll); + + if (y != 0xc75050536) + abort (); + + y = adds_di_test1 (0x5000500050005ll, + 0x2111211121112ll, + 0x0000000002020ll); + if (y != 0x9222922294249) + abort (); + + y = adds_di_test2 (0x130000029ll, + 0x320000004ll, + 0x505050505ll); + if (y != 0x955051532) + abort (); + + y = adds_di_test2 (0x540004100ll, + 0x320000004ll, + 0x805050205ll); + if (y != 0x1065055309) + abort (); + + y = adds_di_test3 (0x130000029ll, + 0x064000008ll, + 0x505050505ll); + if (y != 0x9b9050576) + abort (); + + y = adds_di_test3 (0x130002900ll, + 0x088000008ll, + 0x505050505ll); + if (y != 0xafd052e4d) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ --- gcc/testsuite/gcc.target/aarch64/subs1.c 1970-01-01 05:30:00.000000000 +0530 +++ gcc/testsuite/gcc.target/aarch64/subs1.c 2013-04-01 13:40:48.189390503 +0530 @@ -0,0 +1,149 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps" } */ + +extern void abort (void); + +int +subs_si_test1 (int a, int b, int c) +{ + int d = a - c; + + /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +int +subs_si_test2 (int a, int b, int c) +{ + int d = a - 0xff; + + /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, #255" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +int +subs_si_test3 (int a, int b, int c) +{ + int d = a - (b << 3); + + /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +typedef long long s64; + +s64 +subs_di_test1 (s64 a, s64 b, s64 c) +{ + s64 d = a - c; + + /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +s64 +subs_di_test2 (s64 a, s64 b, s64 c) +{ + s64 d = a - 0xff; + + /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, #255" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +s64 +subs_di_test3 (s64 a, s64 b, s64 c) +{ + s64 d = a - (b << 3); + + /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +int main () +{ + int x; + s64 y; + + x = subs_si_test1 (29, 4, 5); + if (x != 33) + abort (); + + x = subs_si_test1 (5, 2, 20); + if (x != 7) + abort (); + + x = subs_si_test2 (29, 4, 5); + if (x != -217) + abort (); + + x = subs_si_test2 (1024, 2, 20); + if (x != 791) + abort (); + + x = subs_si_test3 (35, 4, 5); + if (x != 12) + abort (); + + x = subs_si_test3 (5, 2, 20); + if (x != 11) + abort (); + + y = subs_di_test1 (0x130000029ll, + 0x320000004ll, + 0x505050505ll); + + if (y != 0x45000002d) + abort (); + + y = subs_di_test1 (0x5000500050005ll, + 0x2111211121112ll, + 0x0000000002020ll); + if (y != 0x7111711171117) + abort (); + + y = subs_di_test2 (0x130000029ll, + 0x320000004ll, + 0x505050505ll); + if (y != 0x955050433) + abort (); + + y = subs_di_test2 (0x130002900ll, + 0x320000004ll, + 0x505050505ll); + if (y != 0x955052d0a) + abort (); + + y = subs_di_test3 (0x130000029ll, + 0x064000008ll, + 0x505050505ll); + if (y != 0x3790504f6) + abort (); + + y = subs_di_test3 (0x130002900ll, + 0x088000008ll, + 0x505050505ll); + if (y != 0x27d052dcd) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ --- gcc/testsuite/gcc.target/aarch64/subs2.c 1970-01-01 05:30:00.000000000 +0530 +++ gcc/testsuite/gcc.target/aarch64/subs2.c 2013-04-01 13:40:48.193390503 +0530 @@ -0,0 +1,155 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps" } */ + +extern void abort (void); + +int +subs_si_test1 (int a, int b, int c) +{ + int d = a - b; + + /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ + /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +int +subs_si_test2 (int a, int b, int c) +{ + int d = a - 0xfff; + + /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, #4095" } } */ + /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, #4095" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +int +subs_si_test3 (int a, int b, int c) +{ + int d = a - (b << 3); + + /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ + /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +typedef long long s64; + +s64 +subs_di_test1 (s64 a, s64 b, s64 c) +{ + s64 d = a - b; + + /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ + /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +s64 +subs_di_test2 (s64 a, s64 b, s64 c) +{ + s64 d = a - 0x1000ll; + + /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, #4096" } } */ + /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, #4096" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +s64 +subs_di_test3 (s64 a, s64 b, s64 c) +{ + s64 d = a - (b << 3); + + /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ + /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +int main () +{ + int x; + s64 y; + + x = subs_si_test1 (29, 4, 5); + if (x != 34) + abort (); + + x = subs_si_test1 (5, 2, 20); + if (x != 25) + abort (); + + x = subs_si_test2 (29, 4, 5); + if (x != 34) + abort (); + + x = subs_si_test2 (1024, 2, 20); + if (x != 1044) + abort (); + + x = subs_si_test3 (35, 4, 5); + if (x != 12) + abort (); + + x = subs_si_test3 (5, 2, 20); + if (x != 25) + abort (); + + y = subs_di_test1 (0x130000029ll, + 0x320000004ll, + 0x505050505ll); + + if (y != 0x63505052e) + abort (); + + y = subs_di_test1 (0x5000500050005ll, + 0x2111211121112ll, + 0x0000000002020ll); + if (y != 0x5000500052025) + abort (); + + y = subs_di_test2 (0x130000029ll, + 0x320000004ll, + 0x505050505ll); + if (y != 0x95504f532) + abort (); + + y = subs_di_test2 (0x540004100ll, + 0x320000004ll, + 0x805050205ll); + if (y != 0x1065053309) + abort (); + + y = subs_di_test3 (0x130000029ll, + 0x064000008ll, + 0x505050505ll); + if (y != 0x63505052e) + abort (); + + y = subs_di_test3 (0x130002900ll, + 0x088000008ll, + 0x505050505ll); + if (y != 0x635052e05) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */