From patchwork Tue Apr 2 04:23:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 232875 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0021B2C00AF for ; Tue, 2 Apr 2013 15:37:55 +1100 (EST) Received: from localhost ([::1]:36955 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMsyo-000390-8R for incoming@patchwork.ozlabs.org; Tue, 02 Apr 2013 00:37:54 -0400 Received: from eggs.gnu.org ([208.118.235.92]:58096) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMsm0-0003cp-Jx for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMslw-0007iI-A5 for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:40 -0400 Received: from mail-yh0-x22f.google.com ([2607:f8b0:4002:c01::22f]:44379) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMslw-0007i9-3Z for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:36 -0400 Received: by mail-yh0-f47.google.com with SMTP id z12so3225yhz.6 for ; Mon, 01 Apr 2013 21:24:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=xCDLvX4xOJOKPpRDpiK1xfBN/gJIRfj1DfRLdjAiv94=; b=W1c9ibH+CQGisZ2kWQET56HU0ZfuMOGo9UCabofKh44/JcRET30kHIVenMriCz+TwB QJCIuJ4TM2xuv/yw19LaV+1n+BK+KHTP8AUmnJ7fmYOW/w79FOIxJNxOUIx1Weh1sdpY YW+67AqdrR2KRd14Aq5nkf/JiWoWVWMpoAq3x8lAYjYaf8eOkLa2DEKGO8r6MdVN177I P6FODnoQ/e0JWKn6ihwYmbooHx3KR5uIJrJdZ0MbuehkQSbTq7w/8NpByI/pg36yQFfl tqYodN5GfCCMIhip3HIdwIXaIxUY3lQZJreBZjdun3M5qK7D5VsSWjdHKqtW7db15f4s tj9Q== X-Received: by 10.236.54.202 with SMTP id i50mr13052924yhc.30.1364876675733; Mon, 01 Apr 2013 21:24:35 -0700 (PDT) Received: from pebble.com ([12.236.175.36]) by mx.google.com with ESMTPS id z64sm32502731yhc.24.2013.04.01.21.24.34 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 01 Apr 2013 21:24:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2013 21:23:27 -0700 Message-Id: <1364876610-3933-25-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1364876610-3933-1-git-send-email-rth@twiddle.net> References: <1364876610-3933-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4002:c01::22f Cc: av1474@comtv.ru, agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v3 24/27] tcg-ppc64: Implement movcond X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++ tcg/ppc64/tcg-target.h | 4 ++-- 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 30954ff..4ade501 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1347,6 +1347,54 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, tcg_out_bc(s, tcg_to_bc[cond], label_index); } +static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, + TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, + TCGArg v2, bool const_c2) +{ + /* If for some reason both inputs are zero, don't produce bad code. */ + if (v1 == 0 && v2 == 0) { + tcg_out_movi(s, type, dest, 0); + return; + } + + tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); + + if (HAVE_ISEL) { + int isel = tcg_to_isel[cond]; + + /* Swap the V operands if the operation indicates inversion. */ + if (isel & 1) { + int t = v1; + v1 = v2; + v2 = t; + isel &= ~1; + } + /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ + if (v2 == 0) { + tcg_out_movi(s, type, 0, 0); + } + tcg_out32(s, isel | TAB(dest, v1, v2)); + } else { + if (dest == v2) { + cond = tcg_invert_cond(cond); + v2 = v1; + } else if (dest != v1) { + if (v1 == 0) { + tcg_out_movi(s, type, dest, 0); + } else { + tcg_out_mov(s, type, dest, v1); + } + } + /* Branch forward over one insn */ + tcg_out32(s, tcg_to_bc[cond] | 8); + if (v2 == 0) { + tcg_out_movi(s, type, dest, 0); + } else { + tcg_out_mov(s, type, dest, v2); + } + } +} + void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr) { TCGContext s; @@ -1895,6 +1943,15 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, 64 - args[3] - args[4]); break; + case INDEX_op_movcond_i32: + tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], + args[3], args[4], const_args[2]); + break; + case INDEX_op_movcond_i64: + tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], + args[3], args[4], const_args[2]); + break; + default: tcg_dump_ops (s); tcg_abort (); @@ -2010,6 +2067,8 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_setcond_i32, { "r", "r", "ri" } }, { INDEX_op_setcond_i64, { "r", "r", "ri" } }, + { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } }, + { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } }, { INDEX_op_bswap16_i32, { "r", "r" } }, { INDEX_op_bswap16_i64, { "r", "r" } }, diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index fed6740..c3a02bb 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -88,7 +88,7 @@ typedef enum { #define TCG_TARGET_HAS_nand_i32 1 #define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_deposit_i32 1 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_add2_i32 0 #define TCG_TARGET_HAS_sub2_i32 0 #define TCG_TARGET_HAS_mulu2_i32 0 @@ -111,7 +111,7 @@ typedef enum { #define TCG_TARGET_HAS_nand_i64 1 #define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_deposit_i64 1 -#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 0 #define TCG_TARGET_HAS_sub2_i64 0 #define TCG_TARGET_HAS_mulu2_i64 0