From patchwork Tue Apr 2 04:23:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 232873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 77DB12C0131 for ; Tue, 2 Apr 2013 15:36:22 +1100 (EST) Received: from localhost ([::1]:34025 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMsxI-0001X6-Nr for incoming@patchwork.ozlabs.org; Tue, 02 Apr 2013 00:36:20 -0400 Received: from eggs.gnu.org ([208.118.235.92]:58024) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMslu-0003Po-4v for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMslo-0007Tu-G1 for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:33 -0400 Received: from mail-gh0-f173.google.com ([209.85.160.173]:47357) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMslo-0007T9-A4 for qemu-devel@nongnu.org; Tue, 02 Apr 2013 00:24:28 -0400 Received: by mail-gh0-f173.google.com with SMTP id g16so2943ghb.18 for ; Mon, 01 Apr 2013 21:24:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=O4P02LBoghrm/sEVx4z9G/ckmff6NDFS6IMgENrEn6M=; b=iWFryrR5NCl6J3LAX2esVdVtvekIxaP4pRMlQENXrP/aOaskVCnQn9jk98BFM3JZ7r B0MkezIXXgsXuifjE3D5x3b3XdYIW7yNLUUH5EDEwmetKgHGVQ/pDQO1sP+NpcBDp0JF lIe7ObM25CzfqOukv4sFXjv3zM52saO54oSxGGzFggK8nSFsMHoz9SHYQJcAlsVRDyAj g0DFKiGmgUiXGtWUqe63rqRWNTTMkDryVHVOP832MjtNHs8i2nhIlomeNYYxy0TTvdg4 qM5P6LdD6FLbym1lD4VKUoUggLVnU+tq1/4xxJz2yRRHGRBR0L7VEuRvfWz/e/WeElPp wsMQ== X-Received: by 10.236.207.34 with SMTP id m22mr13068747yho.31.1364876667812; Mon, 01 Apr 2013 21:24:27 -0700 (PDT) Received: from pebble.com ([12.236.175.36]) by mx.google.com with ESMTPS id z64sm32502731yhc.24.2013.04.01.21.24.26 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 01 Apr 2013 21:24:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2013 21:23:22 -0700 Message-Id: <1364876610-3933-20-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1364876610-3933-1-git-send-email-rth@twiddle.net> References: <1364876610-3933-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.160.173 Cc: av1474@comtv.ru, agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v3 19/27] tcg-ppc64: Handle constant inputs for some compound logicals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since we have special code to handle and/or/xor with a constant, apply the same to andc/orc/eqv with a constant. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 44 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 10 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 392f6a3..9a24d20 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1388,17 +1388,19 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_and_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tcg_out_andi32(s, args[0], args[1], args[2]); + tcg_out_andi32(s, a0, a1, a2); } else { - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_and_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tcg_out_andi64(s, args[0], args[1], args[2]); + tcg_out_andi64(s, a0, a1, a2); } else { - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_or_i64: @@ -1420,14 +1422,36 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_andc_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi32(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } + break; case INDEX_op_andc_i64: - tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi64(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } break; case INDEX_op_orc_i32: + if (const_args[2]) { + tcg_out_ori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ case INDEX_op_orc_i64: tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); break; case INDEX_op_eqv_i32: + if (const_args[2]) { + tcg_out_xori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ case INDEX_op_eqv_i64: tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); break; @@ -1812,9 +1836,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i32, { "r", "r", "ri" } }, { INDEX_op_or_i32, { "r", "r", "ri" } }, { INDEX_op_xor_i32, { "r", "r", "ri" } }, - { INDEX_op_andc_i32, { "r", "r", "r" } }, - { INDEX_op_orc_i32, { "r", "r", "r" } }, - { INDEX_op_eqv_i32, { "r", "r", "r" } }, + { INDEX_op_andc_i32, { "r", "r", "ri" } }, + { INDEX_op_orc_i32, { "r", "r", "ri" } }, + { INDEX_op_eqv_i32, { "r", "r", "ri" } }, { INDEX_op_nand_i32, { "r", "r", "r" } }, { INDEX_op_nor_i32, { "r", "r", "r" } }, @@ -1832,10 +1856,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add_i64, { "r", "r", "rTU" } }, { INDEX_op_sub_i64, { "r", "rI", "rTU" } }, - { INDEX_op_and_i64, { "r", "r", "rU" } }, + { INDEX_op_and_i64, { "r", "r", "ri" } }, { INDEX_op_or_i64, { "r", "r", "rU" } }, { INDEX_op_xor_i64, { "r", "r", "rU" } }, - { INDEX_op_andc_i64, { "r", "r", "r" } }, + { INDEX_op_andc_i64, { "r", "r", "ri" } }, { INDEX_op_orc_i64, { "r", "r", "r" } }, { INDEX_op_eqv_i64, { "r", "r", "r" } }, { INDEX_op_nand_i64, { "r", "r", "r" } },