From patchwork Sun Mar 31 22:34:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 232649 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DC5C02C00C9 for ; Mon, 1 Apr 2013 10:29:43 +1100 (EST) Received: from localhost ([::1]:39341 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQvJ-0006Vb-Q6 for incoming@patchwork.ozlabs.org; Sun, 31 Mar 2013 18:40:25 -0400 Received: from eggs.gnu.org ([208.118.235.92]:32892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQqf-0000Pz-Sq for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMQqc-0007oB-80 for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:37 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:64983) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQqc-0007nu-0T for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:34 -0400 Received: by mail-pa0-f49.google.com with SMTP id kp14so1020110pab.22 for ; Sun, 31 Mar 2013 15:35:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=Z6fuJEz6gr/YsOU2t9STvXDVo+phVdt9KbXHzqqS+BQ=; b=hQ8b10K5d6QCNFwjJKT+IoOpIQYJxAqH/vxgE7liUATSJCdfXu9DrYS3pNFmc6iElq q7Ict/SrXOZk0Wa951G6bXP0iZTxvQ1d/a0KpggmYX2VxI8tk1gpz8VFUk2Mk/td1NNM YM3qghWQzBKPsR7yQXPw3qznmuazD0m/Gs5xGViJg/7SfOZkxXAfzrF570eWxiMWn/df 44JnCiY4+Qx52Aw/A5xWV8MoBSrub2jrDh3i9Hmti3kfD8L5rvB1LrlSKlJDQaQynLwh tF0zzHc+FkktrQAO3RJzjkgxR2t4Gr4f60hBLU+/sqUmLrbtpgu0bvBxVb5lD30pLF1j oxmw== X-Received: by 10.68.196.129 with SMTP id im1mr15052448pbc.206.1364769333342; Sun, 31 Mar 2013 15:35:33 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id ve7sm12586235pab.11.2013.03.31.15.35.31 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 31 Mar 2013 15:35:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 31 Mar 2013 15:34:56 -0700 Message-Id: <1364769305-3687-11-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1364769305-3687-1-git-send-email-rth@twiddle.net> References: <1364769305-3687-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.49 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v5 10/19] tcg-arm: Implement division instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org An armv7 extension implements division, present on Cortex A15. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- disas/arm.c | 4 ++++ tcg/arm/tcg-target.c | 36 ++++++++++++++++++++++++++++++++++++ tcg/arm/tcg-target.h | 7 ++++++- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/disas/arm.c b/disas/arm.c index 4927d8a..76e97a8 100644 --- a/disas/arm.c +++ b/disas/arm.c @@ -819,6 +819,10 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + /* IDIV instructions. */ + {ARM_EXT_DIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_DIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, + /* V7 instructions. */ {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 1044c68..e3d2cfa 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -591,6 +591,16 @@ static inline void tcg_out_smull32(TCGContext *s, } } +static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm) +{ + tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); +} + +static inline void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm) +{ + tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); +} + static inline void tcg_out_ext8s(TCGContext *s, int cond, int rd, int rn) { @@ -1869,6 +1879,25 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, args[3], args[4], const_args[2]); break; + case INDEX_op_div_i32: + tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_divu_i32: + tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_rem_i32: + tcg_out_sdiv(s, COND_AL, TCG_REG_R8, args[1], args[2]); + tcg_out_mul32(s, COND_AL, TCG_REG_R8, TCG_REG_R8, args[2]); + tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_R8, + SHIFT_IMM_LSL(0)); + break; + case INDEX_op_remu_i32: + tcg_out_udiv(s, COND_AL, TCG_REG_R8, args[1], args[2]); + tcg_out_mul32(s, COND_AL, TCG_REG_R8, TCG_REG_R8, args[2]); + tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_R8, + SHIFT_IMM_LSL(0)); + break; + default: tcg_abort(); } @@ -1955,6 +1984,13 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "ri" } }, +#if TCG_TARGET_HAS_div_i32 + { INDEX_op_div_i32, { "r", "r", "r" } }, + { INDEX_op_rem_i32, { "r", "r", "r" } }, + { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_remu_i32, { "r", "r", "r" } }, +#endif + { -1 }, }; diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 209f585..3be41cc 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -56,7 +56,6 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 /* optional instructions */ -#define TCG_TARGET_HAS_div_i32 0 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 0 /* and r0, r1, #0xff */ @@ -75,6 +74,12 @@ typedef enum { #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 +#ifdef __ARM_ARCH_EXT_IDIV__ +#define TCG_TARGET_HAS_div_i32 1 +#else +#define TCG_TARGET_HAS_div_i32 0 +#endif + extern bool tcg_target_deposit_valid(int ofs, int len); #define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid