From patchwork Sun Mar 31 22:34:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 232639 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7E1B92C00D9 for ; Mon, 1 Apr 2013 09:40:38 +1100 (EST) Received: from localhost ([::1]:33377 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQsm-0003J9-OF for incoming@patchwork.ozlabs.org; Sun, 31 Mar 2013 18:37:48 -0400 Received: from eggs.gnu.org ([208.118.235.92]:32879) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQqe-0000NL-7E for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMQqa-0007no-Ct for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:36 -0400 Received: from mail-da0-x234.google.com ([2607:f8b0:400e:c00::234]:43655) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQqa-0007ni-7A for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:32 -0400 Received: by mail-da0-f52.google.com with SMTP id f10so829516dak.11 for ; Sun, 31 Mar 2013 15:35:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=sSoDuY/QSF4w7tfuMjcXPr/MOWLoBENC3f/3TT1hhbs=; b=YzoS5hcs7+IvhOPzcZQ9xmX3Ii82Yqaio3wKdcqt0T5niVwhJIMmb/bwI1VuXCSlAo 4iCKRi/jzzR/7WOPoLG8KdWwuFV1a9jrGqkM+gbtuxmHx5a97nA6IAKv4vhj5sgPp5C9 r04bfG+bJ3xMZSoD018+DYQx+p91RWyt7JjDohnygnzZXfkt5LUikhiQH0mp0nCbQ7Ld 3udO7PS8zwBUhvBggosnLJAgJnruHLPNJfFJQzsyK8CZoKAX3IOJUTzfajuSFje2R4KH Loz9dimILtvwMiwl4uXRWsV/LpM+aIjy20eUoSf0yhawo28Np2lf9pVDmGNlQ7rFuDKu 5QMQ== X-Received: by 10.66.87.234 with SMTP id bb10mr15852085pab.203.1364769331506; Sun, 31 Mar 2013 15:35:31 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id ve7sm12586235pab.11.2013.03.31.15.35.29 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 31 Mar 2013 15:35:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 31 Mar 2013 15:34:55 -0700 Message-Id: <1364769305-3687-10-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1364769305-3687-1-git-send-email-rth@twiddle.net> References: <1364769305-3687-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c00::234 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v5 09/19] tcg-arm: Implement deposit for armv7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We have BFI and BFC available for implementing it. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 36 ++++++++++++++++++++++++++++++++++++ tcg/arm/tcg-target.h | 5 ++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 1f38795..1044c68 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -702,6 +702,35 @@ static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) } } +bool tcg_target_deposit_valid(int ofs, int len) +{ + /* ??? Without bfi, we could improve over generic code by combining + the right-shift from a non-zero ofs with the orr. We do run into + problems when rd == rs, and the mask generated from ofs+len don't + fit into an immediate. We would have to be careful not to pessimize + wrt the optimizations performed on the expanded code. */ + return use_armv7_instructions; +} + +static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len, bool const_a1) +{ + if (const_a1) { + uint32_t mask = (2u << (len - 1)) - 1; + a1 &= mask; + if (a1 == 0) { + /* bfi becomes bfc with rn == 15. */ + a1 = 15; + } else { + tcg_out_movi32(s, cond, TCG_REG_R8, a1); + a1 = TCG_REG_R8; + } + } + /* bfi/bfc */ + tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 + | (ofs << 7) | ((ofs + len - 1) << 16)); +} + static inline void tcg_out_ld32_12(TCGContext *s, int cond, int rd, int rn, tcg_target_long im) { @@ -1835,6 +1864,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext16u(s, COND_AL, args[0], args[1]); break; + case INDEX_op_deposit_i32: + tcg_out_deposit(s, COND_AL, args[0], args[2], + args[3], args[4], const_args[2]); + break; + default: tcg_abort(); } @@ -1919,6 +1953,8 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_ext16s_i32, { "r", "r" } }, { INDEX_op_ext16u_i32, { "r", "r" } }, + { INDEX_op_deposit_i32, { "r", "0", "ri" } }, + { -1 }, }; diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 354dd8a..209f585 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -71,10 +71,13 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_deposit_i32 0 +#define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 +extern bool tcg_target_deposit_valid(int ofs, int len); +#define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid + enum { TCG_AREG0 = TCG_REG_R6, };