From patchwork Sun Mar 31 22:34:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 232637 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CE48A2C0112 for ; Mon, 1 Apr 2013 09:37:35 +1100 (EST) Received: from localhost ([::1]:60475 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQsY-0002gc-13 for incoming@patchwork.ozlabs.org; Sun, 31 Mar 2013 18:37:34 -0400 Received: from eggs.gnu.org ([208.118.235.92]:32813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQqW-0000BX-D6 for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UMQqS-0007lt-U1 for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:28 -0400 Received: from mail-da0-x232.google.com ([2607:f8b0:400e:c00::232]:41242) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UMQqS-0007lj-Ow for qemu-devel@nongnu.org; Sun, 31 Mar 2013 18:35:24 -0400 Received: by mail-da0-f50.google.com with SMTP id t1so823869dae.9 for ; Sun, 31 Mar 2013 15:35:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=GlyH8eWoD88VBHAUQBjd6jxytF0KcyJ47ZX4A4LtjL0=; b=T2gB5hKXDZ+O6BqZln9RiIjNfGbTvnxsfv4U19ej2Dxq1XDFq7Ccgw8JqPf13b9Sgw BawJm+BEdraCA7e0u0RuCkxf4l/0mbTZeapfKqEr0KtApm3uv7xkYqAiVrhmmJyNsOwo QHP3wLPn9wx+fkFkIAexmTQCqXOH8MjhkQJmU0M9ixxVMgSLV8IjE7POHP+c0w101x6e qy9/24RbXFrs0XpSTXcyvvLHs4tlm/tM5Rl2SQjZl/8O8y0tjBlK972PswR2sIiJRkPz dRMXuf1ldIdMVkWItEKsvbQGcbhZL7Ma0v/EBXFpmxW6EzB9NXc/QTYlZJXeB0PE+cCf q+EA== X-Received: by 10.66.164.41 with SMTP id yn9mr15796757pab.93.1364769324046; Sun, 31 Mar 2013 15:35:24 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id ve7sm12586235pab.11.2013.03.31.15.35.22 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 31 Mar 2013 15:35:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 31 Mar 2013 15:34:51 -0700 Message-Id: <1364769305-3687-6-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1364769305-3687-1-git-send-email-rth@twiddle.net> References: <1364769305-3687-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c00::232 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v5 05/19] tcg-arm: Allow constant first argument to sub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This allows the generation of RSB instructions. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index f34828b..a430f1b 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1625,8 +1625,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2], const_args[2]); break; case INDEX_op_sub_i32: - tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, - args[0], args[1], args[2], const_args[2]); + if (const_args[1]) { + if (const_args[2]) { + tcg_out_movi32(s, COND_AL, args[0], args[1] - args[2]); + } else { + tcg_out_dat_rI(s, COND_AL, ARITH_RSB, + args[0], args[2], args[1], 1); + } + } else { + tcg_out_dat_rIN(s, COND_AL, ARITH_SUB, ARITH_ADD, + args[0], args[1], args[2], const_args[2]); + } break; case INDEX_op_and_i32: tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, @@ -1819,7 +1828,7 @@ static const TCGTargetOpDef arm_op_defs[] = { /* TODO: "r", "r", "ri" */ { INDEX_op_add_i32, { "r", "r", "rIN" } }, - { INDEX_op_sub_i32, { "r", "r", "rIN" } }, + { INDEX_op_sub_i32, { "r", "rI", "rIN" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, { INDEX_op_muls2_i32, { "r", "r", "r", "r" } },