From patchwork Sat Mar 30 20:43:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 232562 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6D3AE2C00A9 for ; Sun, 31 Mar 2013 07:47:07 +1100 (EST) Received: from localhost ([::1]:48707 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UM2g5-0007a5-ME for incoming@patchwork.ozlabs.org; Sat, 30 Mar 2013 16:47:05 -0400 Received: from eggs.gnu.org ([208.118.235.92]:34007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UM2dS-00048M-Bs for qemu-devel@nongnu.org; Sat, 30 Mar 2013 16:44:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UM2dO-0005ve-Ov for qemu-devel@nongnu.org; Sat, 30 Mar 2013 16:44:22 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:52652) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UM2dO-0005vX-42 for qemu-devel@nongnu.org; Sat, 30 Mar 2013 16:44:18 -0400 Received: by mail-pa0-f50.google.com with SMTP id bg2so784614pad.9 for ; Sat, 30 Mar 2013 13:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=f+2u3EK0+glRgs+do2xn3J9ifVSAgxOpTRPiWq01oiY=; b=LG3MxocVRHV20X66SXUDWYeqlwKIvTc1iYhwOqJWRJNcop9Nr0ytl42iTr6e5CnUJO E0gBET0IMHtOWDpvTNhMl16IbXTS6gA7UnSsUD8+3Q/PpW7H5MppNw5G2OyC7GB5jzw3 fgN0twuJ96Ug9N4sXC7hCrDNFusJ5xEjYUUyIJ5nxBc3u+wfnEMlvodsufl2tc+0c6t4 paORBSDjFdP0L62N/0EsU2YGfPsl01RNxD+vY8wPoLH6IZSaVyHDaq0PFFd68Ii0kdby 6iefw4qUsquhBhaNhQQWIXKTeuxIfjw19JPmXhWve3l/Mw66dNnDg0akRn8KBnTL6qNa hYjg== X-Received: by 10.68.180.227 with SMTP id dr3mr10327583pbc.56.1364676257340; Sat, 30 Mar 2013 13:44:17 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id gf1sm7620362pbc.24.2013.03.30.13.44.15 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 30 Mar 2013 13:44:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 30 Mar 2013 13:43:23 -0700 Message-Id: <1364676207-21516-15-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1364676207-21516-1-git-send-email-rth@twiddle.net> References: <1364676207-21516-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.50 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v4 14/18] tcg-arm: Split out tcg_out_tlb_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Share code between qemu_ld and qemu_st to process the tlb. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 169 +++++++++++++++++++++------------------------------ 1 file changed, 70 insertions(+), 99 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 4ad4849..50819ec 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1148,40 +1148,15 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, argreg = tcg_out_arg_reg32(s, argreg, arghi); return argreg; } -#endif /* SOFTMMU */ #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) -static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) -{ - int addr_reg, data_reg, data_reg2, bswap; -#ifdef CONFIG_SOFTMMU - int mem_index, s_bits, tlb_offset; - TCGReg argreg; -# if TARGET_LONG_BITS == 64 - int addr_reg2; -# endif - uint32_t *label_ptr; -#endif - -#ifdef TARGET_WORDS_BIGENDIAN - bswap = 1; -#else - bswap = 0; -#endif - data_reg = *args++; - if (opc == 3) - data_reg2 = *args++; - else - data_reg2 = 0; /* suppress warning */ - addr_reg = *args++; -#ifdef CONFIG_SOFTMMU -# if TARGET_LONG_BITS == 64 - addr_reg2 = *args++; -# endif - mem_index = *args; - s_bits = opc & 3; +/* Load and compare a TLB entry, leaving the flags set. Leaves R0 pointing + to the tlb entry. Clobbers R1 and TMP. */ +static void tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, + int s_bits, int tlb_offset) +{ /* Should generate something like the following: * shr r8, addr_reg, #TARGET_PAGE_BITS * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8 @@ -1191,13 +1166,13 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) # error # endif tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, - 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); tcg_out_dat_imm(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); + /* We assume that the offset is contained within 20 bits. */ - tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read); assert((tlb_offset & ~0xfffff) == 0); if (tlb_offset > 0xfff) { tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0, @@ -1207,16 +1182,48 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset); tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + /* Check alignment. */ - if (s_bits) + if (s_bits) { tcg_out_dat_imm(s, COND_EQ, ARITH_TST, - 0, addr_reg, (1 << s_bits) - 1); -# if TARGET_LONG_BITS == 64 - /* XXX: possibly we could use a block data load in the first access. */ - tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4); - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, - TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0)); -# endif + 0, addrlo, (1 << s_bits) - 1); + } + + if (TARGET_LONG_BITS == 64) { + /* XXX: possibly we could use a block data load in the first access. */ + tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4); + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, + TCG_REG_R1, addrhi, SHIFT_IMM_LSL(0)); + } +} +#endif /* SOFTMMU */ + +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) +{ + TCGReg addr_reg, data_reg, data_reg2; + bool bswap; +#ifdef CONFIG_SOFTMMU + int mem_index, s_bits; + TCGReg argreg, addr_reg2; + uint32_t *label_ptr; +#endif +#ifdef TARGET_WORDS_BIGENDIAN + bswap = 1; +#else + bswap = 0; +#endif + + data_reg = *args++; + data_reg2 = (opc == 3 ? *args++ : 0); + addr_reg = *args++; +#ifdef CONFIG_SOFTMMU + addr_reg2 = (TARGET_LONG_BITS == 64 ? *args++ : 0); + mem_index = *args; + s_bits = opc & 3; + + tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits, + offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)); + tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, offsetof(CPUTLBEntry, addend) - offsetof(CPUTLBEntry, addr_read)); @@ -1272,11 +1279,11 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) */ argreg = TCG_REG_R0; argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0); -#if TARGET_LONG_BITS == 64 - argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2); -#else - argreg = tcg_out_arg_reg32(s, argreg, addr_reg); -#endif + if (TARGET_LONG_BITS == 64) { + argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2); + } else { + argreg = tcg_out_arg_reg32(s, argreg, addr_reg); + } argreg = tcg_out_arg_imm32(s, argreg, mem_index); tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[s_bits]); @@ -1303,8 +1310,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) #else /* !CONFIG_SOFTMMU */ if (GUEST_BASE) { uint32_t offset = GUEST_BASE; - int i; - int rot; + int i, rot; while (offset) { i = ctz32(offset) & ~1; @@ -1363,68 +1369,33 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) #endif } -static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) { - int addr_reg, data_reg, data_reg2, bswap; + TCGReg addr_reg, data_reg, data_reg2; + bool bswap; #ifdef CONFIG_SOFTMMU - int mem_index, s_bits, tlb_offset; - TCGReg argreg; -# if TARGET_LONG_BITS == 64 - int addr_reg2; -# endif + int mem_index, s_bits; + TCGReg argreg, addr_reg2; uint32_t *label_ptr; #endif - #ifdef TARGET_WORDS_BIGENDIAN bswap = 1; #else bswap = 0; #endif + data_reg = *args++; - if (opc == 3) - data_reg2 = *args++; - else - data_reg2 = 0; /* suppress warning */ + data_reg2 = (opc == 3 ? *args++ : 0); addr_reg = *args++; #ifdef CONFIG_SOFTMMU -# if TARGET_LONG_BITS == 64 - addr_reg2 = *args++; -# endif + addr_reg2 = (TARGET_LONG_BITS == 64 ? *args++ : 0); mem_index = *args; s_bits = opc & 3; - /* Should generate something like the following: - * shr r8, addr_reg, #TARGET_PAGE_BITS - * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8 - * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS - */ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, - TCG_REG_TMP, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); - tcg_out_dat_imm(s, COND_AL, ARITH_AND, - TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, - TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); - /* We assume that the offset is contained within 20 bits. */ - tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write); - assert((tlb_offset & ~0xfffff) == 0); - if (tlb_offset > 0xfff) { - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0, - 0xa00 | (tlb_offset >> 12)); - tlb_offset &= 0xfff; - } - tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset); - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1, - TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); - /* Check alignment. */ - if (s_bits) - tcg_out_dat_imm(s, COND_EQ, ARITH_TST, - 0, addr_reg, (1 << s_bits) - 1); -# if TARGET_LONG_BITS == 64 - /* XXX: possibly we could use a block data load in the first access. */ - tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4); - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, - TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0)); -# endif + tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits, + offsetof(CPUArchState, + tlb_table[mem_index][0].addr_write)); + tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, offsetof(CPUTLBEntry, addend) - offsetof(CPUTLBEntry, addr_write)); @@ -1473,11 +1444,11 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) */ argreg = TCG_REG_R0; argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0); -#if TARGET_LONG_BITS == 64 - argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2); -#else - argreg = tcg_out_arg_reg32(s, argreg, addr_reg); -#endif + if (TARGET_LONG_BITS == 64) { + argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2); + } else { + argreg = tcg_out_arg_reg32(s, argreg, addr_reg); + } switch (opc) { case 0: