From patchwork Sat Mar 30 20:43:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 232558 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DF0732C009F for ; Sun, 31 Mar 2013 07:44:52 +1100 (EST) Received: from localhost ([::1]:41933 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UM2dv-0003rn-1t for incoming@patchwork.ozlabs.org; Sat, 30 Mar 2013 16:44:51 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33906) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UM2dD-0003eQ-3k for qemu-devel@nongnu.org; Sat, 30 Mar 2013 16:44:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UM2d9-0005sU-Fk for qemu-devel@nongnu.org; Sat, 30 Mar 2013 16:44:07 -0400 Received: from mail-pb0-f43.google.com ([209.85.160.43]:62132) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UM2d9-0005sE-AI for qemu-devel@nongnu.org; Sat, 30 Mar 2013 16:44:03 -0400 Received: by mail-pb0-f43.google.com with SMTP id md4so673565pbc.16 for ; Sat, 30 Mar 2013 13:44:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=WOoCaAwkhCVmF6kZGMsVvOeoF7hcIY2UB70qnPBmqRA=; b=0SQyGQgW0r4aYkFB+wELWwPDHhZ9lAQHpfbNcyV3s9sqoEvGJ/+jW1wbT9nSx8WHSB uXASVP0+oUUTr2OABv7wcVG4uuzDGk7tDginQoWrOZVP5Lb/cwMFLalR7Z9KjTMfH3bp iFUeRsFjWwwd18NsOeIV/LjYl7THijROR8o3j8YlNsdZsgsi6mfqVgb6EjoMo8klnd37 eJBL0cnE1jM2nfTteEq+X7W7njhO8Kwh3b6Pfpm+1X3shySlzckLnm75doDY03+p7O3A TKZv0Irp9nEsZ/VmO45Ztw7jnXQg6nCNxzKRl6jLOu5tUEWuH9wIEyPYv3CMdqzDNru4 59Iw== X-Received: by 10.68.197.193 with SMTP id iw1mr10461528pbc.86.1364676242614; Sat, 30 Mar 2013 13:44:02 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id gf1sm7620362pbc.24.2013.03.30.13.44.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sat, 30 Mar 2013 13:44:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 30 Mar 2013 13:43:17 -0700 Message-Id: <1364676207-21516-9-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1364676207-21516-1-git-send-email-rth@twiddle.net> References: <1364676207-21516-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.160.43 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v4 08/18] tcg-arm: Implement deposit for armv7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We have BFI and BFC available for implementing it. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 36 ++++++++++++++++++++++++++++++++++++ tcg/arm/tcg-target.h | 5 ++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index ca76902..313a6cf 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -702,6 +702,35 @@ static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) } } +bool tcg_target_deposit_valid(int ofs, int len) +{ + /* ??? Without bfi, we could improve over generic code by combining + the right-shift from a non-zero ofs with the orr. We do run into + problems when rd == rs, and the mask generated from ofs+len don't + fit into an immediate. We would have to be careful not to pessimize + wrt the optimizations performed on the expanded code. */ + return use_armv7_instructions; +} + +static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd, + TCGArg a1, int ofs, int len, bool const_a1) +{ + if (const_a1) { + uint32_t mask = (2u << (len - 1)) - 1; + a1 &= mask; + if (a1 == 0) { + /* bfi becomes bfc with rn == 15. */ + a1 = 15; + } else { + tcg_out_movi32(s, cond, TCG_REG_R8, a1); + a1 = TCG_REG_R8; + } + } + /* bfi/bfc */ + tcg_out32(s, 0x07c00010 | (cond << 28) | (rd << 12) | a1 + | (ofs << 7) | ((ofs + len - 1) << 16)); +} + static inline void tcg_out_ld32_12(TCGContext *s, int cond, int rd, int rn, tcg_target_long im) { @@ -1835,6 +1864,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext16u(s, COND_AL, args[0], args[1]); break; + case INDEX_op_deposit_i32: + tcg_out_deposit(s, COND_AL, args[0], args[2], + args[3], args[4], const_args[2]); + break; + default: tcg_abort(); } @@ -1919,6 +1953,8 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_ext16s_i32, { "r", "r" } }, { INDEX_op_ext16u_i32, { "r", "r" } }, + { INDEX_op_deposit_i32, { "r", "0", "ri" } }, + { -1 }, }; diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 354dd8a..209f585 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -71,10 +71,13 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 -#define TCG_TARGET_HAS_deposit_i32 0 +#define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 +extern bool tcg_target_deposit_valid(int ofs, int len); +#define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid + enum { TCG_AREG0 = TCG_REG_R6, };