Patchwork [10/10] -fuse-caller-save - Add test-case

login
register
mail settings
Submitter Tom de Vries
Date March 30, 2013, 5:12 p.m.
Message ID <20130330171215.890B6421213@build1-lucid-cs>
Download mbox | patch
Permalink /patch/232542/
State New
Headers show

Comments

Tom de Vries - March 30, 2013, 5:12 p.m.
Richard,

This patch series adds analysis of register usage of functions for usage by IRA.
The original post is here
( http://gcc.gnu.org/ml/gcc-patches/2013-01/msg01234.html ).

This patch adds a test-case for -fuse-caller-save.  Since the test-case has
different output for mips16 and micromips, new effective targets are introduced.

Build and reg-tested on mips.

OK for trunk?

Thanks,
  -Tom

2013-03-30  Radovan Obradovic  <robradovic@mips.com>
            Tom de Vries  <tom@codesourcery.com>

	* lib/target-supports.exp (check_effective_target_mips16)
	(check_effective_target_micromips): New proc.
	* gcc.target/mips/mips.exp: Add use-caller-save to -ffoo/-fno-foo
	options.  Add -save-temps to mips_option_groups.
	* gcc.target/mips/aru-1.c: New test.
Richard Sandiford - April 27, 2013, 10:01 a.m.
Tom de Vries <tom@codesourcery.com> writes:
> +/* { dg-do run } */
> +/* { dg-options "-fuse-caller-save -save-temps" } */
> +/* { dg-skip-if "" { *-*-* }  { "*" } { "-Os" } } */
> +/* Testing -fuse-caller-save optimization option.  */
> +
> +static int __attribute__((noinline))
> +bar (int x)
> +{
> +  return x + 3;
> +}
> +
> +int __attribute__((noinline))
> +foo (int y)
> +{
> +  return y + bar (y);
> +}
> +
> +int
> +main (void)
> +{
> +  return !(foo (5) == 13);
> +}
> +
> +/* Check that there are only 2 stack-saves: r31 in main and foo.  */
> +
> +/* Variant not mips16.  Check that there only 2 sw/sd.  */
> +/* { dg-final { scan-assembler-times "(?n)s\[wd\]\t\\\$.*,.*\\(\\\$sp\\)" 2 { target { ! mips16 } } } } */
> +
> +/* Variant not mips16, Subvariant micromips.  Additionally check there's no
> +   swm.  */
> +/* { dg-final { scan-assembler-times "(?n)swm\t\\\$.*,.*\\(\\\$sp\\)" 0 {target micromips } } } */
> +
> +/* Variant mips16.  The save can save 1 or more registers, check that only 1 is
> +   saved, twice in total.  */
> +/* { dg-final { scan-assembler-times "(?n)save\t\[0-9\]*,\\\$\[^,\]*\$" 2 { target mips16 } } } */
> +
> +/* Check that the first caller-save register is unused.  */
> +/* { dg-final { scan-assembler-not "(\\\$16)" } } */

Sorry to ask, but I think it would be better to split this up into
a compile test and a run test.  The run test shouldn't be skipped at -Os.
It should probably also go somewhere more general than gcc.target/mips.

I've tried to avoid conditional scan-assemblers in gcc.target/mips
whereever possible.  The directory has been set up so that you can force
any subtarget you like, so that (for example) -mips16 output is tested
by every run, not just things like mips-sim/-mips16.

In this case I think that means using NOCOMPRESSION to force the
functions to use the standard ISA encoding and making the scan-assemblers
test only for that.  Since you've already done the work :-), bonus points
for creating two copies, one for micromips (dg-options "-micromips ...")
and one for mips16 (dg-options "-mips16 ...").  That's certainly not a
requirement though.

Thanks,
Richard

Patch

diff --git a/gcc/testsuite/gcc.target/mips/aru-1.c b/gcc/testsuite/gcc.target/mips/aru-1.c
new file mode 100644
index 0000000..71515a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/aru-1.c
@@ -0,0 +1,38 @@ 
+/* { dg-do run } */
+/* { dg-options "-fuse-caller-save -save-temps" } */
+/* { dg-skip-if "" { *-*-* }  { "*" } { "-Os" } } */
+/* Testing -fuse-caller-save optimization option.  */
+
+static int __attribute__((noinline))
+bar (int x)
+{
+  return x + 3;
+}
+
+int __attribute__((noinline))
+foo (int y)
+{
+  return y + bar (y);
+}
+
+int
+main (void)
+{
+  return !(foo (5) == 13);
+}
+
+/* Check that there are only 2 stack-saves: r31 in main and foo.  */
+
+/* Variant not mips16.  Check that there only 2 sw/sd.  */
+/* { dg-final { scan-assembler-times "(?n)s\[wd\]\t\\\$.*,.*\\(\\\$sp\\)" 2 { target { ! mips16 } } } } */
+
+/* Variant not mips16, Subvariant micromips.  Additionally check there's no
+   swm.  */
+/* { dg-final { scan-assembler-times "(?n)swm\t\\\$.*,.*\\(\\\$sp\\)" 0 {target micromips } } } */
+
+/* Variant mips16.  The save can save 1 or more registers, check that only 1 is
+   saved, twice in total.  */
+/* { dg-final { scan-assembler-times "(?n)save\t\[0-9\]*,\\\$\[^,\]*\$" 2 { target mips16 } } } */
+
+/* Check that the first caller-save register is unused.  */
+/* { dg-final { scan-assembler-not "(\\\$16)" } } */
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
index 15b1386..63570bd 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -246,6 +246,7 @@  set mips_option_groups {
     small-data "-G[0-9]+"
     warnings "-w"
     dump "-fdump-.*"
+    save_temps "-save-temps"
 }
 
 # Add -mfoo/-mno-foo options to mips_option_groups.
@@ -302,6 +303,7 @@  foreach option {
     tree-vectorize
     unroll-all-loops
     unroll-loops
+    use-caller-save
 } {
     lappend mips_option_groups $option "-f(no-|)$option"
 }
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index a146f17..dbd0037 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -918,6 +918,26 @@  proc check_effective_target_mips16_attribute { } {
     } [add_options_for_mips16_attribute ""]]
 }
 
+# Return 1 if the target generates mips16 code by default.
+
+proc check_effective_target_mips16 { } {
+    return [check_no_compiler_messages mips16 assembly {
+	#if !(defined __mips16)
+	#error FOO
+	#endif
+    } ""]
+}
+
+# Return 1 if the target generates micromips code by default.
+
+proc check_effective_target_micromips { } {
+    return [check_no_compiler_messages micromips assembly {
+	#if !(defined __mips_micromips)
+	#error FOO
+	#endif
+    } ""]
+}
+
 # Return 1 if the target supports long double larger than double when
 # using the new ABI, 0 otherwise.