From patchwork Sat Mar 30 02:16:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 232503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D9CF12C00CF for ; Sat, 30 Mar 2013 13:17:10 +1100 (EST) Received: from localhost ([::1]:57863 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULlLx-0005Yq-1r for incoming@patchwork.ozlabs.org; Fri, 29 Mar 2013 22:17:09 -0400 Received: from eggs.gnu.org ([208.118.235.92]:45953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULlLV-0005V0-Se for qemu-devel@nongnu.org; Fri, 29 Mar 2013 22:16:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ULlLU-0008Si-7k for qemu-devel@nongnu.org; Fri, 29 Mar 2013 22:16:41 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:40207) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULlLU-0008SV-1L for qemu-devel@nongnu.org; Fri, 29 Mar 2013 22:16:40 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1ULlLT-0006ra-9U; Sat, 30 Mar 2013 03:16:39 +0100 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1ULlLS-0004SV-9u; Sat, 30 Mar 2013 03:16:38 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 30 Mar 2013 03:16:30 +0100 Message-Id: <1364609794-16753-2-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1364609794-16753-1-git-send-email-aurelien@aurel32.net> References: <1364609794-16753-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 1/5] target-i386: add pclmulqdq instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-i386/cpu.c | 19 +++++++++---------- target-i386/ops_sse.h | 24 ++++++++++++++++++++++++ target-i386/ops_sse_header.h | 5 +++++ target-i386/translate.c | 3 +++ 4 files changed, 41 insertions(+), 10 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 4b43759..41382c5 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -387,17 +387,16 @@ typedef struct x86_def_t { CPUID_PSE36 (needed for Solaris) */ /* missing: CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ -#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \ - CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | \ - CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | \ - CPUID_EXT_HYPERVISOR) +#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ + CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ + CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ + CPUID_EXT_MOVBE | CPUID_EXT_HYPERVISOR) /* missing: - CPUID_EXT_PCLMULQDQ, CPUID_EXT_DTES64, CPUID_EXT_DSCPL, - CPUID_EXT_VMX, CPUID_EXT_SMX, CPUID_EXT_EST, CPUID_EXT_TM2, - CPUID_EXT_CID, CPUID_EXT_FMA, CPUID_EXT_XTPR, CPUID_EXT_PDCM, - CPUID_EXT_PCID, CPUID_EXT_DCA, CPUID_EXT_X2APIC, - CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AES, CPUID_EXT_XSAVE, - CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C, + CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, + CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, + CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, + CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AES, + CPUID_EXT_XSAVE, CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C, CPUID_EXT_RDRAND */ #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ diff --git a/target-i386/ops_sse.h b/target-i386/ops_sse.h index a11dba1..2ee5b8d 100644 --- a/target-i386/ops_sse.h +++ b/target-i386/ops_sse.h @@ -2179,6 +2179,30 @@ target_ulong helper_popcnt(CPUX86State *env, target_ulong n, uint32_t type) return POPCOUNT(n, 5); #endif } + +void glue(helper_pclmulqdq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, + uint32_t ctrl) +{ + uint64_t ah, al, b, resh, resl; + + ah = 0; + al = d->Q((ctrl & 1) != 0); + b = s->Q((ctrl & 16) != 0); + resh = resl = 0; + + while (b) { + if (b & 1) { + resl ^= al; + resh ^= ah; + } + ah = (ah << 1) | (al >> 63); + al <<= 1; + b >>= 1; + } + + d->Q(0) = resl; + d->Q(1) = resh; +} #endif #undef SHIFT diff --git a/target-i386/ops_sse_header.h b/target-i386/ops_sse_header.h index 401eac6..2842233 100644 --- a/target-i386/ops_sse_header.h +++ b/target-i386/ops_sse_header.h @@ -336,6 +336,11 @@ DEF_HELPER_3(crc32, tl, i32, tl, i32) DEF_HELPER_3(popcnt, tl, env, tl, i32) #endif +/* AES-NI op helpers */ +#if SHIFT == 1 +DEF_HELPER_4(glue(pclmulqdq, SUFFIX), void, env, Reg, Reg, i32) +#endif + #undef SHIFT #undef Reg #undef SUFFIX diff --git a/target-i386/translate.c b/target-i386/translate.c index 7596a90..d649e99 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -3147,6 +3147,8 @@ struct SSEOpHelper_eppi { #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 } #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 } #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 } +#define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \ + CPUID_EXT_PCLMULQDQ } static const struct SSEOpHelper_epp sse_op_table6[256] = { [0x00] = SSSE3_OP(pshufb), @@ -3216,6 +3218,7 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = { [0x40] = SSE41_OP(dpps), [0x41] = SSE41_OP(dppd), [0x42] = SSE41_OP(mpsadbw), + [0x44] = PCLMULQDQ_OP(pclmulqdq), [0x60] = SSE42_OP(pcmpestrm), [0x61] = SSE42_OP(pcmpestri), [0x62] = SSE42_OP(pcmpistrm),