Patchwork microblaze: Add support for the sleep insn

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Submitter Edgar Iglesias
Date March 29, 2013, 9:44 p.m.
Message ID <1364593471-26730-1-git-send-email-edgar.iglesias@gmail.com>
Download mbox | patch
Permalink /patch/232495/
State New
Headers show

Comments

Edgar Iglesias - March 29, 2013, 9:44 p.m.
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-microblaze/translate.c |   15 +++++++++++++++
 1 file changed, 15 insertions(+)
Blue Swirl - March 30, 2013, 1:45 p.m.
On Fri, Mar 29, 2013 at 9:44 PM,  <edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target-microblaze/translate.c |   15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index a74da8e..21a7119 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -1317,6 +1317,21 @@ static void dec_br(DisasContext *dc)
>      /* Memory barrier.  */
>      mbar = (dc->ir >> 16) & 31;
>      if (mbar == 2 && dc->imm == 4) {
> +        /* mbar IMM & 16 decodes to sleep.  */
> +        if (dc->rd & 16) {
> +            TCGv_i32 tmp = tcg_const_i32(EXCP_HLT);
> +
> +            LOG_DIS("sleep\n");
> +
> +            t_sync_flags(dc);
> +            tcg_gen_st_i32(tcg_const_i32(1), cpu_env,

This leaks the result of tcg_const_i32(1).

> +                           -offsetof(MicroBlazeCPU, env)
> +                           +offsetof(CPUState, halted));
> +            tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
> +            gen_helper_raise_exception(cpu_env, tmp);
> +            tcg_temp_free_i32(tmp);
> +            return;
> +        }
>          LOG_DIS("mbar %d\n", dc->rd);
>          /* Break the TB.  */
>          dc->cpustate_changed = 1;
> --
> 1.7.9.5
>
>
Edgar Iglesias - March 30, 2013, 2:13 p.m.
On Sat, Mar 30, 2013 at 01:45:26PM +0000, Blue Swirl wrote:
> On Fri, Mar 29, 2013 at 9:44 PM,  <edgar.iglesias@gmail.com> wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> >  target-microblaze/translate.c |   15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> > index a74da8e..21a7119 100644
> > --- a/target-microblaze/translate.c
> > +++ b/target-microblaze/translate.c
> > @@ -1317,6 +1317,21 @@ static void dec_br(DisasContext *dc)
> >      /* Memory barrier.  */
> >      mbar = (dc->ir >> 16) & 31;
> >      if (mbar == 2 && dc->imm == 4) {
> > +        /* mbar IMM & 16 decodes to sleep.  */
> > +        if (dc->rd & 16) {
> > +            TCGv_i32 tmp = tcg_const_i32(EXCP_HLT);
> > +
> > +            LOG_DIS("sleep\n");
> > +
> > +            t_sync_flags(dc);
> > +            tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
> 
> This leaks the result of tcg_const_i32(1).

Fixed in v2, thanks

Edgar

Patch

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index a74da8e..21a7119 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1317,6 +1317,21 @@  static void dec_br(DisasContext *dc)
     /* Memory barrier.  */
     mbar = (dc->ir >> 16) & 31;
     if (mbar == 2 && dc->imm == 4) {
+        /* mbar IMM & 16 decodes to sleep.  */
+        if (dc->rd & 16) {
+            TCGv_i32 tmp = tcg_const_i32(EXCP_HLT);
+
+            LOG_DIS("sleep\n");
+
+            t_sync_flags(dc);
+            tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
+                           -offsetof(MicroBlazeCPU, env)
+                           +offsetof(CPUState, halted));
+            tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
+            gen_helper_raise_exception(cpu_env, tmp);
+            tcg_temp_free_i32(tmp);
+            return;
+        }
         LOG_DIS("mbar %d\n", dc->rd);
         /* Break the TB.  */
         dc->cpustate_changed = 1;