Patchwork [U-Boot] Tegra: Configure L2 cache control reg properly.

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Submitter Tom Warren
Date March 29, 2013, 8:38 p.m.
Message ID <1364589490-2759-1-git-send-email-twarren@nvidia.com>
Download mbox | patch
Permalink /patch/232492/
State Accepted
Delegated to: Tom Warren
Headers show

Comments

Tom Warren - March 29, 2013, 8:38 p.m.
Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.

Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/tegra-common/Makefile   |  2 +-
 arch/arm/cpu/tegra-common/ap.c       |  9 ++-----
 arch/arm/cpu/tegra-common/cache.c    | 48 ++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra/ap.h |  1 +
 4 files changed, 52 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/cpu/tegra-common/cache.c
Stephen Warren - March 29, 2013, 10:43 p.m.
On 03/29/2013 02:38 PM, Tom Warren wrote:
> Without this change, kernel fails at calling function cache_clean_flush
> during kernel early boot.
> 
> Aprocryphally, intended for T114 only, so I check for a T114 SoC.
> Works (i.e. dalmore 3.8 kernel now starts printing to console).

I don't know enough about the caches to really review this, but I have
no particular objection to it. My one comment is ...

> diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c

> +void config_cache(void)

> +	/* Currently, only T114 needs this L2 cache change to boot Linux */
> +	reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
> +	if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
> +		return;

Can we introduce a standard function for that instead? We already have
tegra_get_chip_type() which returns a SKU-based ID. I think we need to
introduce a tegra_get_soc_type() that returns a pure Tegra20/30/114
value, and probably use this in most places we currently use the result
of tegra_get_chip_type(), since most care about SW-compatibility of
features rather than SKU which drivers performance levels instead
typically. Then, perhaps rename tegra_get_chip_type() to
tegra_get_soc_sku() and re-write it to use tegra_get_soc_type()?
Tom Warren - March 29, 2013, 11:32 p.m.
Stephen,


On Fri, Mar 29, 2013 at 3:43 PM, Stephen Warren <swarren@wwwdotorg.org>wrote:

> On 03/29/2013 02:38 PM, Tom Warren wrote:
> > Without this change, kernel fails at calling function cache_clean_flush
> > during kernel early boot.
> >
> > Aprocryphally, intended for T114 only, so I check for a T114 SoC.
> > Works (i.e. dalmore 3.8 kernel now starts printing to console).
>
> I don't know enough about the caches to really review this, but I have
> no particular objection to it. My one comment is ...
>
> > diff --git a/arch/arm/cpu/tegra-common/cache.c
> b/arch/arm/cpu/tegra-common/cache.c
>
> > +void config_cache(void)
>
> > +     /* Currently, only T114 needs this L2 cache change to boot Linux */
> > +     reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
> > +     if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
> > +             return;
>
> Can we introduce a standard function for that instead? We already have
> tegra_get_chip_type() which returns a SKU-based ID. I think we need to
> introduce a tegra_get_soc_type() that returns a pure Tegra20/30/114
> value, and probably use this in most places we currently use the result
> of tegra_get_chip_type(), since most care about SW-compatibility of
> features rather than SKU which drivers performance levels instead
> typically. Then, perhaps rename tegra_get_chip_type() to
> tegra_get_soc_sku() and re-write it to use tegra_get_soc_type()?
>

I can do that, but I'd prefer to do it as a separate patch since
tegra_get_chip_type is used in a few other places.

This patch is needed by a customer to get their kernel loading (or at least
past the 'Decompressing Linux...' part). I'll correct this patch later to
use tegra_get_soc_type().

Thanks,

Tom

Patch

diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile
index 8e95c7e..4e0301c 100644
--- a/arch/arm/cpu/tegra-common/Makefile
+++ b/arch/arm/cpu/tegra-common/Makefile
@@ -28,7 +28,7 @@  include $(TOPDIR)/config.mk
 LIB	= $(obj)libcputegra-common.o
 
 SOBJS += lowlevel_init.o
-COBJS-y	+= ap.o board.o sys_info.o timer.o clock.o
+COBJS-y	+= ap.o board.o sys_info.o timer.o clock.o cache.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 3f30805..a739fe2 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -139,11 +139,6 @@  void s_init(void)
 
 	enable_scu();
 
-	/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
-	asm volatile(
-		"mrc	p15, 0, r0, c1, c0, 1\n"
-		"orr	r0, r0, #0x41\n"
-		"mcr	p15, 0, r0, c1, c0, 1\n");
-
-	/* FIXME: should have SoC's L2 disabled too? */
+	/* init the cache */
+	config_cache();
 }
diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c
new file mode 100644
index 0000000..48e9319
--- /dev/null
+++ b/arch/arm/cpu/tegra-common/cache.c
@@ -0,0 +1,48 @@ 
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra cache routines */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch/gp_padctrl.h>
+
+void config_cache(void)
+{
+	struct apb_misc_gp_ctlr *gp =
+		(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+	u32 reg = 0;
+
+	/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
+	asm volatile(
+		"mrc p15, 0, r0, c1, c0, 1\n"
+		"orr r0, r0, #0x41\n"
+		"mcr p15, 0, r0, c1, c0, 1\n");
+
+	/* Currently, only T114 needs this L2 cache change to boot Linux */
+	reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
+	if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
+		return;
+	/*
+	 * Systems with an architectural L2 cache must not use the PL310.
+	 * Config L2CTLR here for a data RAM latency of 3 cycles.
+	 */
+	asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
+	reg &= ~7;
+	reg |= 2;
+	asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
+}
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
index 73dfd39..5999f55 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -64,3 +64,4 @@  extern void _start(void);
  * @return	SOC type - see TEGRA_SOC...
  */
 int tegra_get_chip_type(void);
+void config_cache(void);