From patchwork Thu Mar 28 19:54:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varun Sethi X-Patchwork-Id: 232177 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id AFD682C083B for ; Fri, 29 Mar 2013 07:05:12 +1100 (EST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe002.messaging.microsoft.com [216.32.181.182]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id F3B122C019B for ; Fri, 29 Mar 2013 07:02:32 +1100 (EST) Received: from mail231-ch1-R.bigfish.com (10.43.68.236) by CH1EHSOBE002.bigfish.com (10.43.70.52) with Microsoft SMTP Server id 14.1.225.23; Thu, 28 Mar 2013 20:02:28 +0000 Received: from mail231-ch1 (localhost [127.0.0.1]) by mail231-ch1-R.bigfish.com (Postfix) with ESMTP id 48A93E4006C; Thu, 28 Mar 2013 20:02:28 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzd799hzz1f42h1fc6h1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1155h) Received: from mail231-ch1 (localhost.localdomain [127.0.0.1]) by mail231-ch1 (MessageSwitch) id 136450094657529_32466; Thu, 28 Mar 2013 20:02:26 +0000 (UTC) Received: from CH1EHSMHS032.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.243]) by mail231-ch1.bigfish.com (Postfix) with ESMTP id EE24EB8005F; Thu, 28 Mar 2013 20:02:25 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS032.bigfish.com (10.43.70.32) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 28 Mar 2013 20:02:23 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.328.11; Thu, 28 Mar 2013 20:02:22 +0000 Received: from nmglablinux27.zin33.ap.freescale.net (nmglablinux28.zin33.ap.freescale.net [10.232.20.211]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r2SK1qsM032605; Thu, 28 Mar 2013 13:02:18 -0700 From: Varun Sethi To: , , , , , , , Subject: [PATCH 4/5 v11] iommu/fsl: Add additional iommu attributes required by the PAMU driver. Date: Fri, 29 Mar 2013 01:24:01 +0530 Message-ID: <1364500442-20927-5-git-send-email-Varun.Sethi@freescale.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1364500442-20927-1-git-send-email-Varun.Sethi@freescale.com> References: <1364500442-20927-1-git-send-email-Varun.Sethi@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Varun Sethi X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Added the following domain attributes for the FSL PAMU driver: 1. Added new iommu stash attribute, which allows setting of the LIODN specific stash id parameter through IOMMU API. 2. Added an attribute for enabling/disabling DMA to a particular memory window. 3. Added domain attribute to check for PAMUV1 specific constraints. Signed-off-by: Varun Sethi --- - no change in v11. - no change in v10. include/linux/iommu.h | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 2727810..af8f996 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -40,6 +40,25 @@ struct notifier_block; typedef int (*iommu_fault_handler_t)(struct iommu_domain *, struct device *, unsigned long, int, void *); +/* cache stash targets */ +enum stash_target { + IOMMU_ATTR_CACHE_L1 = 1, + IOMMU_ATTR_CACHE_L2, + IOMMU_ATTR_CACHE_L3, +}; + +/* This attribute corresponds to IOMMUs capable of generating + * a stash transaction. A stash transaction is typically a + * hardware initiated prefetch of data from memory to cache. + * This attribute allows configuring stashig specific parameters + * in the IOMMU hardware. + */ + +struct iommu_stash_attribute { + u32 cpu; /* cpu number */ + u32 cache; /* cache to stash to: L1,L2,L3 */ +}; + struct iommu_domain_geometry { dma_addr_t aperture_start; /* First address that can be mapped */ dma_addr_t aperture_end; /* Last address that can be mapped */ @@ -57,10 +76,26 @@ struct iommu_domain { #define IOMMU_CAP_CACHE_COHERENCY 0x1 #define IOMMU_CAP_INTR_REMAP 0x2 /* isolates device intrs */ +/* + * Following constraints are specifc to PAMUV1: + * -aperture must be power of 2, and naturally aligned + * -number of windows must be power of 2, and address space size + * of each window is determined by aperture size / # of windows + * -the actual size of the mapped region of a window must be power + * of 2 starting with 4KB and physical address must be naturally + * aligned. + * DOMAIN_ATTR_FSL_PAMUV1 corresponds to the above mentioned contraints. + * The caller can invoke iommu_domain_get_attr to check if the underlying + * iommu implementation supports these constraints. + */ + enum iommu_attr { DOMAIN_ATTR_GEOMETRY, DOMAIN_ATTR_PAGING, DOMAIN_ATTR_WINDOWS, + DOMAIN_ATTR_PAMU_STASH, + DOMAIN_ATTR_PAMU_ENABLE, + DOMAIN_ATTR_FSL_PAMUV1, DOMAIN_ATTR_MAX, };