From patchwork Thu Mar 28 17:22:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Shawcroft X-Patchwork-Id: 232142 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id BCEA42C00A8 for ; Fri, 29 Mar 2013 04:24:06 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=e8foGKHjOEMqvs83G 0b5saafzcJ6CCgnzPSCIMMdczOWDNQlC2j0vYkfGAXhFoMt3ZpVpV+TyyXGgLqut 5VK4zgiaCF22PvCbRuy16j1qiOhFLMfWNyc7huqfNrJTGTUj52mRtNo5mtzI7tEa DpFJzWWiJMUFA2OA2I4TvJsoUE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=FS3e5UOAf+FNjpqWBBiYIpj DQIs=; b=x0Qx19lNlwGauJeddz4lwMMDwkmNyepKWIRWKfz7XNeAk1rNrE20kkb 3VDAfLLHH+LSZexQHvijzG/v75KHUH6G1twHoDyD2K3ZtIJS5tn+nI8nBFgbmmwN DyRHdct1i70tNp3RPrDaWJBuot1eOkBd6TIaqAQuRDHNxVlvkr80= Received: (qmail 17198 invoked by alias); 28 Mar 2013 17:23:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16873 invoked by uid 89); 28 Mar 2013 17:22:59 -0000 X-Spam-SWARE-Status: No, score=-2.9 required=5.0 tests=AWL, BAYES_00, KHOP_RCVD_UNTRUST, KHOP_THREADED, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Thu, 28 Mar 2013 17:22:56 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Thu, 28 Mar 2013 17:22:53 +0000 Received: from [10.1.72.50] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 28 Mar 2013 17:22:51 +0000 Message-ID: <51547C6B.7050908@arm.com> Date: Thu, 28 Mar 2013 17:22:51 +0000 From: Marcus Shawcroft User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130221 Thunderbird/17.0.3 MIME-Version: 1.0 To: "Hurugalawadi, Naveen" CC: Ian Bolton , "gcc-patches@gcc.gnu.org" Subject: Re: [PING^1] [AArch64] Implement Bitwise AND and Set Flags References: , <000c01ce2180$0864b030$192e1090$@bolton@arm.com>, In-Reply-To: X-MC-Unique: 113032817225322101 X-Virus-Found: No On 26/03/13 11:35, Hurugalawadi, Naveen wrote: > Hi, > >>> >>Can we split them into two different patches. Just and in one > Thanks for reviewing the patch. I have split the patches for "and" > separately as per your suggestion. Thanks, I've adjusted the patch to use the SHIFT iterator instead of ASHIFT and committed as attached. Ian, has a BICS implementation to follow which will include his testcase as previously posted for both ANDS and BICS. /Marcus diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index ca94d70..4f04081 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2467,6 +2467,69 @@ [(set_attr "v8type" "logic,logic_imm") (set_attr "mode" "SI")]) +(define_insn "*and3_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (match_operand:GPI 1 "register_operand" "%r,r") + (match_operand:GPI 2 "aarch64_logical_operand" "r,")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r,r") + (and:GPI (match_dup 1) (match_dup 2)))] + "" + "ands\\t%0, %1, %2" + [(set_attr "v8type" "logics,logics_imm") + (set_attr "mode" "")] +) + +;; zero_extend version of above +(define_insn "*andsi3_compare0_uxtw" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:SI (match_operand:SI 1 "register_operand" "%r,r") + (match_operand:SI 2 "aarch64_logical_operand" "r,K")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] + "" + "ands\\t%w0, %w1, %w2" + [(set_attr "v8type" "logics,logics_imm") + (set_attr "mode" "SI")] +) + +(define_insn "*and_3_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (SHIFT:GPI + (match_operand:GPI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_" "n")) + (match_operand:GPI 3 "register_operand" "r")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (and:GPI (SHIFT:GPI (match_dup 1) (match_dup 2)) (match_dup 3)))] + "" + "ands\\t%0, %3, %1, %2" + [(set_attr "v8type" "logics_shift") + (set_attr "mode" "")] +) + +;; zero_extend version of above +(define_insn "*and_si3_compare0_uxtw" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:SI (SHIFT:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_si" "n")) + (match_operand:SI 3 "register_operand" "r")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (and:SI (SHIFT:SI (match_dup 1) (match_dup 2)) + (match_dup 3))))] + "" + "ands\\t%w0, %w3, %w1, %2" + [(set_attr "v8type" "logics_shift") + (set_attr "mode" "SI")] +) + (define_insn "*_3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (SHIFT:GPI