From patchwork Thu Mar 28 15:32:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 232082 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C414E2C00C2 for ; Fri, 29 Mar 2013 02:50:32 +1100 (EST) Received: from localhost ([::1]:34016 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULEs5-0004SM-WA for incoming@patchwork.ozlabs.org; Thu, 28 Mar 2013 11:36:10 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57337) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULEpb-00016B-3r for qemu-devel@nongnu.org; Thu, 28 Mar 2013 11:33:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ULEpY-0003ZQ-5I for qemu-devel@nongnu.org; Thu, 28 Mar 2013 11:33:34 -0400 Received: from mail-da0-x232.google.com ([2607:f8b0:400e:c00::232]:53195) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULEpX-0003Yg-TX for qemu-devel@nongnu.org; Thu, 28 Mar 2013 11:33:32 -0400 Received: by mail-da0-f50.google.com with SMTP id t1so3021208dae.23 for ; Thu, 28 Mar 2013 08:33:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=ATWVgr60gRhGOmqHwTOWvAQu5mspEDouuTCbVlFamnI=; b=ThzNdDeH19IseuFoEFHoW538xVpCB5ClcX5lrxmzyk0DjAHdyYKpb3VwZJ0UEBhQJX S3gEZhQsKpG6yVs7DH9/hEgJpfzTJfyLGSRdHb1xNCrAoCZw7wfW2n9VIyOta2Xz4Xzq Efw9p/6BWLiizGYGW67jlCDDVTq6SUT3E0mpapnL9tkXwYHZvCR294rxmKLAgcBTr/WM S4T1cgk2RtPExmUN8tprtX/P7LaxxNxyPuZUdFW3vfAB2RpKxwKYSyp57BfD/R36K/FT R1gIjY/gtTnqC+jOC4rgK8EYV6Ghp+6NS+FDOS31WRwzREgcz9Zsbcr77jLW2Zdtvt6S Kv7Q== X-Received: by 10.66.121.169 with SMTP id ll9mr15933307pab.178.1364484810753; Thu, 28 Mar 2013 08:33:30 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id kb3sm25939542pbc.21.2013.03.28.08.33.28 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 28 Mar 2013 08:33:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2013 08:32:50 -0700 Message-Id: <1364484781-15561-10-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1364484781-15561-1-git-send-email-rth@twiddle.net> References: <1364484781-15561-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c00::232 Cc: Peter Maydell , Aurelien Jarno Subject: [Qemu-devel] [PATCH v3 09/20] tcg-arm: Implement division instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org An armv7 extension implements division, present on Cortex A15. Signed-off-by: Richard Henderson --- disas/arm.c | 4 ++++ tcg/arm/tcg-target.c | 36 ++++++++++++++++++++++++++++++++++++ tcg/arm/tcg-target.h | 7 ++++++- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/disas/arm.c b/disas/arm.c index 4927d8a..76e97a8 100644 --- a/disas/arm.c +++ b/disas/arm.c @@ -819,6 +819,10 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + /* IDIV instructions. */ + {ARM_EXT_DIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_EXT_DIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, + /* V7 instructions. */ {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 4950eaf..e599794 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -591,6 +591,16 @@ static inline void tcg_out_smull32(TCGContext *s, } } +static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int rm) +{ + tcg_out32(s, 0x0710f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); +} + +static inline void tcg_out_udiv(TCGContext *s, int cond, int rd, int rn, int rm) +{ + tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); +} + static inline void tcg_out_ext8s(TCGContext *s, int cond, int rd, int rn) { @@ -1907,6 +1917,25 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, args[3], args[4], const_args[2]); break; + case INDEX_op_div_i32: + tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_divu_i32: + tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); + break; + case INDEX_op_rem_i32: + tcg_out_sdiv(s, COND_AL, TCG_REG_R8, args[1], args[2]); + tcg_out_mul32(s, COND_AL, TCG_REG_R8, TCG_REG_R8, args[2]); + tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_R8, + SHIFT_IMM_LSL(0)); + break; + case INDEX_op_remu_i32: + tcg_out_udiv(s, COND_AL, TCG_REG_R8, args[1], args[2]); + tcg_out_mul32(s, COND_AL, TCG_REG_R8, TCG_REG_R8, args[2]); + tcg_out_dat_reg(s, COND_AL, ARITH_SUB, args[0], args[1], TCG_REG_R8, + SHIFT_IMM_LSL(0)); + break; + default: tcg_abort(); } @@ -1993,6 +2022,13 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "ri" } }, +#if TCG_TARGET_HAS_div_i32 + { INDEX_op_div_i32, { "r", "r", "r" } }, + { INDEX_op_rem_i32, { "r", "r", "r" } }, + { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_remu_i32, { "r", "r", "r" } }, +#endif + { -1 }, }; diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 209f585..3be41cc 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -56,7 +56,6 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 /* optional instructions */ -#define TCG_TARGET_HAS_div_i32 0 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 0 /* and r0, r1, #0xff */ @@ -75,6 +74,12 @@ typedef enum { #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 +#ifdef __ARM_ARCH_EXT_IDIV__ +#define TCG_TARGET_HAS_div_i32 1 +#else +#define TCG_TARGET_HAS_div_i32 0 +#endif + extern bool tcg_target_deposit_valid(int ofs, int len); #define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid