From patchwork Thu Mar 28 15:37:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 232079 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2A0002C00CB for ; Fri, 29 Mar 2013 02:43:08 +1100 (EST) Received: from localhost ([::1]:47533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULEyo-0003qE-DW for incoming@patchwork.ozlabs.org; Thu, 28 Mar 2013 11:43:06 -0400 Received: from eggs.gnu.org ([208.118.235.92]:58396) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULEu5-0006pH-9i for qemu-devel@nongnu.org; Thu, 28 Mar 2013 11:38:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ULEu2-0005G9-3O for qemu-devel@nongnu.org; Thu, 28 Mar 2013 11:38:13 -0400 Received: from mail-pd0-f173.google.com ([209.85.192.173]:62199) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ULEu1-0005Fy-K0 for qemu-devel@nongnu.org; Thu, 28 Mar 2013 11:38:09 -0400 Received: by mail-pd0-f173.google.com with SMTP id v10so4174141pde.4 for ; Thu, 28 Mar 2013 08:38:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=hDETRV5+7yY4kZ+F+5Q5h5/5ckPoRwcIm2/khb6afys=; b=n5xjNghPOB0LYVLkQ2meUp9NUvGgpwZWL+QrAntff/TWhd9Pd0iXIOLX8OUC4wAJZN lLkOqs1/us75hNTw+DithkFGqgpBYUe7AflXLdn3nc1xevEloEjT2CBNNFoBP2ylBh8d h//K0826Ozhq27985hi7jEouQuwdLYnZMqCD0icN2vKutE6C9uZyjOr66YdfdWncrQFz aWlXxKWHFwEOBEXOZaU41xJp4eqHLQCh+TdsJDuTLkSTJOgr1rXQn2VY+upxz6MRUKwz FQTo7w69xvh0Vl58f0i3Wo8joG3OsKnSV5a9RQnEXcoFJGd/tWUjSQc9npOaGHiVTxm5 nFVA== X-Received: by 10.68.240.103 with SMTP id vz7mr35755041pbc.171.1364485088872; Thu, 28 Mar 2013 08:38:08 -0700 (PDT) Received: from pebble.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id cn1sm11022925pbb.7.2013.03.28.08.38.07 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 28 Mar 2013 08:38:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Mar 2013 08:37:55 -0700 Message-Id: <1364485075-17899-6-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1364485075-17899-1-git-send-email-rth@twiddle.net> References: <1364485075-17899-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.192.173 Cc: Stefan Weil Subject: [Qemu-devel] [PATCH 5/5] tci: Make tcg temporaries local to tcg_qemu_tb_exec X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We're moving away from the temporaries stored in env. Make sure we can differentiate between temp stores and possibly bogus stores for extra call arguments. Move TCG_AREG0 and TCG_REG_CALL_STACK out of the way of the parameter passing registers. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c | 12 ++++++------ tcg/tci/tcg-target.h | 8 +++++++- tci.c | 6 ++++++ 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c index b096a84..d1241b5 100644 --- a/tcg/tci/tcg-target.c +++ b/tcg/tci/tcg-target.c @@ -40,11 +40,6 @@ /* Bitfield n...m (in 32 bit value). */ #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) -/* Used for function call generation. */ -#define TCG_REG_CALL_STACK TCG_REG_R4 -#define TCG_TARGET_STACK_ALIGN 16 -#define TCG_TARGET_CALL_STACK_OFFSET 0 - /* Macros used in tcg_target_op_defs. */ #define R "r" #define RI "ri" @@ -901,10 +896,15 @@ static void tcg_target_init(TCGContext *s) /* TODO: Which registers should be set here? */ tcg_regset_set32(tcg_target_call_clobber_regs, 0, BIT(TCG_TARGET_NB_REGS) - 1); + tcg_regset_clear(s->reserved_regs); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); tcg_add_target_add_op_defs(tcg_target_op_defs); - tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf), + + /* We use negative offsets from "sp" so that we can distinguish + stores that might pretend to be call arguments. */ + tcg_set_frame(s, TCG_REG_CALL_STACK, + -CPU_TEMP_BUF_NLONGS * sizeof(long), CPU_TEMP_BUF_NLONGS * sizeof(long)); } diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 1f17576..0395bbb 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -127,7 +127,6 @@ typedef enum { TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, - TCG_AREG0 = TCG_REG_R7, #if TCG_TARGET_NB_REGS >= 16 TCG_REG_R8, TCG_REG_R9, @@ -160,6 +159,13 @@ typedef enum { TCG_CONST = UINT8_MAX } TCGReg; +#define TCG_AREG0 (TCG_TARGET_NB_REGS - 2) + +/* Used for function call generation. */ +#define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1) +#define TCG_TARGET_CALL_STACK_OFFSET 0 +#define TCG_TARGET_STACK_ALIGN 16 + void tci_disas(uint8_t opc); tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); diff --git a/tci.c b/tci.c index 70f8308..c742c8d 100644 --- a/tci.c +++ b/tci.c @@ -112,6 +112,7 @@ static void tci_write_reg(TCGReg index, tcg_target_ulong value) { assert(index < ARRAY_SIZE(tci_reg)); assert(index != TCG_AREG0); + assert(index != TCG_REG_CALL_STACK); tci_reg[index] = value; } @@ -435,9 +436,12 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) /* Interpret pseudo code in tb. */ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) { + long tcg_temps[CPU_TEMP_BUF_NLONGS]; + uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); tcg_target_ulong next_tb = 0; tci_reg[TCG_AREG0] = (tcg_target_ulong)env; + tci_reg[TCG_REG_CALL_STACK] = sp_value; assert(tb_ptr); for (;;) { @@ -585,6 +589,7 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t0 = tci_read_r32(&tb_ptr); t1 = tci_read_r(&tb_ptr); t2 = tci_read_s32(&tb_ptr); + assert(t1 != sp_value || (int32_t)t2 < 0); *(uint32_t *)(t1 + t2) = t0; break; @@ -869,6 +874,7 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t0 = tci_read_r64(&tb_ptr); t1 = tci_read_r(&tb_ptr); t2 = tci_read_s32(&tb_ptr); + assert(t1 != sp_value || (int32_t)t2 < 0); *(uint64_t *)(t1 + t2) = t0; break;