[U-Boot,V2] arm: omap: emif: Fix DDR3 init after warm reset

Submitted by Lokesh Vutla on March 28, 2013, 6:24 a.m.

Details

Message ID 1364451882-6518-1-git-send-email-lokeshvutla@ti.com
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Lokesh Vutla March 28, 2013, 6:24 a.m.
EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.

Tested on OMAP5432 ES2.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
Changes since V1:
	- Changed $subject
	- Removed redundant in_sdram check
 arch/arm/cpu/armv7/omap-common/emif-common.c |   11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

Comments

Tom Rini April 29, 2013, 8:21 p.m.
On Wed, Mar 27, 2013 at 08:24:42PM -0000, Lokesh Vutla wrote:

> EMIF supports a global warm reset mode, during which the
> EMIF keeps the SDRAM content. But if leveling is enabled
> at the time of warm reset for DDR3, the following steps
> needs to be done after warm reset:
> 1) Keep EMIF in self refresh mode.
> 2) Reset PHY to bring back the PHY to a known state.
> 3) Start Levelling procedure.
> Doing the same.
> And also enabling DLL lock and code output after warm reset.
> 
> Tested on OMAP5432 ES2.0
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Applied to u-boot-ti/master, thanks!

Patch hide | download patch | download mbox

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 9eb1279..3e3f3ea 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1072,6 +1072,11 @@  static void do_sdram_init(u32 base)
 		else
 			ddr3_init(base, regs);
 	}
+	if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+		set_lpmode_selfrefresh(base);
+		emif_reset_phy(base);
+		ddr3_leveling(base, regs);
+	}
 
 	/* Write to the shadow registers */
 	emif_update_timings(base, regs);
@@ -1259,10 +1264,10 @@  void sdram_init(void)
 	in_sdram = running_from_sdram();
 	debug("in_sdram = %d\n", in_sdram);
 
-	if (!(in_sdram || warm_reset())) {
-		if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+	if (!in_sdram) {
+		if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
 			bypass_dpll((*prcm)->cm_clkmode_dpll_core);
-		else
+		else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
 			writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
 	}