From patchwork Tue Mar 26 22:05:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mihai Caraman X-Patchwork-Id: 231558 X-Patchwork-Delegate: agust@denx.de Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 3EDB82C0506 for ; Wed, 27 Mar 2013 09:07:22 +1100 (EST) Received: from tx2outboundpool.messaging.microsoft.com (tx2ehsobe003.messaging.microsoft.com [65.55.88.13]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id A40FF2C01C8 for ; Wed, 27 Mar 2013 09:06:04 +1100 (EST) Received: from mail75-tx2-R.bigfish.com (10.9.14.227) by TX2EHSOBE004.bigfish.com (10.9.40.24) with Microsoft SMTP Server id 14.1.225.23; Tue, 26 Mar 2013 22:05:57 +0000 Received: from mail75-tx2 (localhost [127.0.0.1]) by mail75-tx2-R.bigfish.com (Postfix) with ESMTP id 96F062E0107; Tue, 26 Mar 2013 22:05:57 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1155h) Received: from mail75-tx2 (localhost.localdomain [127.0.0.1]) by mail75-tx2 (MessageSwitch) id 136433553711765_12467; Tue, 26 Mar 2013 22:05:37 +0000 (UTC) Received: from TX2EHSMHS038.bigfish.com (unknown [10.9.14.251]) by mail75-tx2.bigfish.com (Postfix) with ESMTP id F2C8220130; Tue, 26 Mar 2013 22:05:36 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS038.bigfish.com (10.9.99.138) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 26 Mar 2013 22:05:36 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.328.11; Tue, 26 Mar 2013 22:05:36 +0000 Received: from mcaraman-VirtualBox.ea.freescale.net (mcaraman-VirtualBox.ea.freescale.net [10.171.73.14]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r2QM5LeN007004; Tue, 26 Mar 2013 15:05:34 -0700 From: Mihai Caraman To: Subject: [PATCH 5/7 v2] KVM: PPC: e500: Remove E.PT and E.HV.LRAT categories from VCPUs Date: Wed, 27 Mar 2013 00:05:10 +0200 Message-ID: <1364335512-28426-6-git-send-email-mihai.caraman@freescale.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1364335512-28426-1-git-send-email-mihai.caraman@freescale.com> References: <1364335512-28426-1-git-send-email-mihai.caraman@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Mihai Caraman , linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Embedded.Page Table (E.PT) category in VMs requires indirect tlb entries emulation which is not supported yet. Configure TLBnCFG to remove E.PT and E.HV.LRAT categories from VCPUs. Signed-off-by: Mihai Caraman --- v2: - Remove E.HV.LRAT from vcpus arch/powerpc/kvm/e500_mmu.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c index cf60db1..0d2a293 100644 --- a/arch/powerpc/kvm/e500_mmu.c +++ b/arch/powerpc/kvm/e500_mmu.c @@ -867,11 +867,17 @@ static int vcpu_mmu_init(struct kvm_vcpu *vcpu, vcpu->arch.tlbcfg[1] |= params[1].ways << TLBnCFG_ASSOC_SHIFT; if (has_feature(vcpu, VCPU_FTR_MMU_V2)) { + vcpu->arch.mmucfg &= ~MMUCFG_LRAT; + if (has_feature(vcpu, VCPU_FTR_E_PT)) vcpu->arch.eptcfg = mfspr(SPRN_EPTCFG); else vcpu->arch.eptcfg = 0; + /* Guest mmu emulation currently doesn't handle E.PT */ + vcpu->arch.tlbcfg[0] &= ~TLBnCFG_PT; + vcpu->arch.tlbcfg[1] &= ~TLBnCFG_IND; + vcpu->arch.tlbps[0] = mfspr(SPRN_TLB0PS); vcpu->arch.tlbps[1] = mfspr(SPRN_TLB1PS); }