Patchwork [5/7,v2] KVM: PPC: e500: Remove E.PT and E.HV.LRAT categories from VCPUs

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Submitter Mihai Caraman
Date March 26, 2013, 10:05 p.m.
Message ID <1364335512-28426-6-git-send-email-mihai.caraman@freescale.com>
Download mbox | patch
Permalink /patch/231550/
State New
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Comments

Mihai Caraman - March 26, 2013, 10:05 p.m.
Embedded.Page Table (E.PT) category in VMs requires indirect tlb entries
emulation which is not supported yet. Configure TLBnCFG to remove E.PT
and E.HV.LRAT categories from VCPUs.

Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
---
v2:
 - Remove E.HV.LRAT from vcpus

 arch/powerpc/kvm/e500_mmu.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)
Alexander Graf - March 27, 2013, 5:23 p.m.
On 26.03.2013, at 23:05, Mihai Caraman wrote:

> Embedded.Page Table (E.PT) category in VMs requires indirect tlb entries
> emulation which is not supported yet. Configure TLBnCFG to remove E.PT
> and E.HV.LRAT categories from VCPUs.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> v2:
> - Remove E.HV.LRAT from vcpus
> 
> arch/powerpc/kvm/e500_mmu.c |    6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
> index cf60db1..0d2a293 100644
> --- a/arch/powerpc/kvm/e500_mmu.c
> +++ b/arch/powerpc/kvm/e500_mmu.c
> @@ -867,11 +867,17 @@ static int vcpu_mmu_init(struct kvm_vcpu *vcpu,
> 	vcpu->arch.tlbcfg[1] |= params[1].ways << TLBnCFG_ASSOC_SHIFT;
> 
> 	if (has_feature(vcpu, VCPU_FTR_MMU_V2)) {
> +		vcpu->arch.mmucfg &= ~MMUCFG_LRAT;
> +
> 		if (has_feature(vcpu, VCPU_FTR_E_PT))
> 			vcpu->arch.eptcfg = mfspr(SPRN_EPTCFG);
> 		else
> 			vcpu->arch.eptcfg = 0;
> 
> +		/* Guest mmu emulation currently doesn't handle E.PT */
> +		vcpu->arch.tlbcfg[0] &= ~TLBnCFG_PT;
> +		vcpu->arch.tlbcfg[1] &= ~TLBnCFG_IND;

Can we make this conditional on bits in EPTCFG? Then by initializing it to 0 today, we always mask PT/IND out, but later when we support EPT, we only have to set the bit in EPTCFG and everyone's happy?


Alex

> +
> 		vcpu->arch.tlbps[0] = mfspr(SPRN_TLB0PS);
> 		vcpu->arch.tlbps[1] = mfspr(SPRN_TLB1PS);
> 	}
> -- 
> 1.7.4.1
> 
> 
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Scott Wood - March 27, 2013, 5:50 p.m.
On 03/26/2013 05:05:10 PM, Mihai Caraman wrote:
> Embedded.Page Table (E.PT) category in VMs requires indirect tlb  
> entries
> emulation which is not supported yet. Configure TLBnCFG to remove E.PT
> and E.HV.LRAT categories from VCPUs.
> 
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> v2:
>  - Remove E.HV.LRAT from vcpus
> 
>  arch/powerpc/kvm/e500_mmu.c |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
> index cf60db1..0d2a293 100644
> --- a/arch/powerpc/kvm/e500_mmu.c
> +++ b/arch/powerpc/kvm/e500_mmu.c
> @@ -867,11 +867,17 @@ static int vcpu_mmu_init(struct kvm_vcpu *vcpu,
>  	vcpu->arch.tlbcfg[1] |= params[1].ways << TLBnCFG_ASSOC_SHIFT;
> 
>  	if (has_feature(vcpu, VCPU_FTR_MMU_V2)) {
> +		vcpu->arch.mmucfg &= ~MMUCFG_LRAT;
> +
>  		if (has_feature(vcpu, VCPU_FTR_E_PT))
>  			vcpu->arch.eptcfg = mfspr(SPRN_EPTCFG);
>  		else
>  			vcpu->arch.eptcfg = 0;
> 
> +		/* Guest mmu emulation currently doesn't handle E.PT */
> +		vcpu->arch.tlbcfg[0] &= ~TLBnCFG_PT;
> +		vcpu->arch.tlbcfg[1] &= ~TLBnCFG_IND;

You're clearing these bits *after* calling has_feature() -- doesn't  
has_feature() depend on those bits being cleared to not advertise E_PT  
support?

-Scott
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Patch

diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index cf60db1..0d2a293 100644
--- a/arch/powerpc/kvm/e500_mmu.c
+++ b/arch/powerpc/kvm/e500_mmu.c
@@ -867,11 +867,17 @@  static int vcpu_mmu_init(struct kvm_vcpu *vcpu,
 	vcpu->arch.tlbcfg[1] |= params[1].ways << TLBnCFG_ASSOC_SHIFT;
 
 	if (has_feature(vcpu, VCPU_FTR_MMU_V2)) {
+		vcpu->arch.mmucfg &= ~MMUCFG_LRAT;
+
 		if (has_feature(vcpu, VCPU_FTR_E_PT))
 			vcpu->arch.eptcfg = mfspr(SPRN_EPTCFG);
 		else
 			vcpu->arch.eptcfg = 0;
 
+		/* Guest mmu emulation currently doesn't handle E.PT */
+		vcpu->arch.tlbcfg[0] &= ~TLBnCFG_PT;
+		vcpu->arch.tlbcfg[1] &= ~TLBnCFG_IND;
+
 		vcpu->arch.tlbps[0] = mfspr(SPRN_TLB0PS);
 		vcpu->arch.tlbps[1] = mfspr(SPRN_TLB1PS);
 	}