Patchwork [01/10] target-i386: SSE4.1: fix pinsrb instruction

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Submitter Aurelien Jarno
Date March 26, 2013, 7:01 p.m.
Message ID <1364324502-9124-2-git-send-email-aurelien@aurel32.net>
Download mbox | patch
Permalink /patch/231521/
State New
Headers show

Comments

Aurelien Jarno - March 26, 2013, 7:01 p.m.
gen_op_mov_TN_reg() loads the value in cpu_T[0], so this temporary should
be used instead of cpu_tmp0.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-i386/translate.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
Richard Henderson - March 27, 2013, 8:03 p.m.
On 03/26/2013 12:01 PM, Aurelien Jarno wrote:
> gen_op_mov_TN_reg() loads the value in cpu_T[0], so this temporary should
> be used instead of cpu_tmp0.
> 
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target-i386/translate.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Patch

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7239696..7596a90 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4404,9 +4404,9 @@  static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                     if (mod == 3)
                         gen_op_mov_TN_reg(OT_LONG, 0, rm);
                     else
-                        tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
+                        tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0,
                                         (s->mem_index >> 2) - 1);
-                    tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
+                    tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
                                             xmm_regs[reg].XMM_B(val & 15)));
                     break;
                 case 0x21: /* insertps */