Patchwork [AArch64] Bitwise adds and subs instructions with shift

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Submitter Hurugalawadi, Naveen
Date March 26, 2013, 11:42 a.m.
Message ID <F3068DEED1A463459E0887A091B15493123546F4@BY2PRD0710MB364.namprd07.prod.outlook.com>
Download mbox | patch
Permalink /patch/231182/
State New
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Comments

Hurugalawadi, Naveen - March 26, 2013, 11:42 a.m.
Hi,

Please find attached the patch that implements adds and subs 
instructions with shift for aarch64 target.
Testcase have been added for adds and subs instructions similar to
the "and" testcase provided by Ian.

Please review the same and let me know if there should be any 
modifications in the patch.
 
Build and tested on aarch64-thunder-elf (using Cavium's internal
simulator). No new regressions.

Thanks,
Naveen

gcc/

2013-03-26   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/aarch64/aarch64.md (*add<mode>3_compare0): Use stack
	register in constraint of 1st operand along with general registers.
	(*addsi3_compare0_uxtw): Likewise.
	(*sub<mode>3_compare0): Likewise.
	(*subsi3_compare0_uxtw): Likewise.
	(*adds_<shift>_<mode>, *adds_<shift>_si_uxtw): New pattern.
	(*adds_mul_imm_<mode>, *adds_mul_imm_si_uxtw): New pattern.
	(*subs_<shift>_<mode>, *subs_<shift>_si_uxtw): New pattern.
	(*subs_mul_imm_<mode>, *subs_mul_imm_si_uxtw): New pattern.

gcc/testsuite/

2013-03-26   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gcc.target/aarch64/adds1.c: New.
	* gcc.target/aarch64/adds2.c: New.
	* gcc.target/aarch64/subs1.c: New.
	* gcc.target/aarch64/subs2.c: New.
Marcus Shawcroft - March 28, 2013, 6:36 p.m.
Hi,

I'm not sure how good the coverage is from these test cases
On 26/03/13 11:42, Hurugalawadi, Naveen wrote:

>   (define_insn "*add<mode>3_compare0"
>     [(set (reg:CC_NZ CC_REGNUM)
>   	(compare:CC_NZ
> -	 (plus:GPI (match_operand:GPI 1 "register_operand" "%r,r")
> +	 (plus:GPI (match_operand:GPI 1 "register_operand" "%rk,rk")
>   		   (match_operand:GPI 2 "aarch64_plus_operand" "rI,J"))

SP is not valid for ADDS shifted register form.

>   (define_insn "*addsi3_compare0_uxtw"
>     [(set (reg:CC_NZ CC_REGNUM)
>   	(compare:CC_NZ
> -	 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
> +	 (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk")
>   		  (match_operand:SI 2 "aarch64_plus_operand" "rI,J"))

Likewise.

> +(define_insn "*adds_<shift>_<mode>"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +	(compare:CC_NZ
> +	 (plus:GPI (ASHIFT:GPI
> +		    (match_operand:GPI 1 "register_operand" "r")
> +		    (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
> +		   (match_operand:GPI 3 "register_operand" "r"))
> +	 (const_int 0)))
> +   (set (match_operand:GPI 0 "register_operand" "=r")
> +	(plus:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))
> +		  (match_dup 3)))]
> +  ""
> +  "adds\\t%<w>0, %<w>3, %<w>1, <shift> %2"
> +  [(set_attr "v8type" "alu_shift")

alus_shift


Looking at the output from the tests supplied below, I don;t think this 
pattern is tested.

> +   (set_attr "mode" "<MODE>")]
> +)
> +
> +;; zero_extend version of above
> +(define_insn "*adds_<shift>_si_uxtw"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +	(compare:CC_NZ
> +	 (plus:SI (ASHIFT:SI
> +		   (match_operand:SI 1 "register_operand" "r")
> +		   (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
> +		  (match_operand:SI 3 "register_operand" "r"))
> +	 (const_int 0)))
> +   (set (match_operand:DI 0 "register_operand" "=r")
> +	(zero_extend:DI (plus:SI (ASHIFT:SI (match_dup 1) (match_dup 2))
> +				 (match_dup 3))))]
> +  ""
> +  "adds\\t%w0, %w3, %w1, <shift> %2"
> +  [(set_attr "v8type" "alu_shift")

alus_shift

Likewise, does the test case below hit this pattern?


> +(define_insn "*adds_mul_imm_<mode>"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +	(compare:CC_NZ
> +	 (plus:GPI (mult:GPI
> +		    (match_operand:GPI 1 "register_operand" "r")
> +		    (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
> +		   (match_operand:GPI 3 "register_operand" "rk"))
> +	 (const_int 0)))
> +   (set (match_operand:GPI 0 "register_operand" "=r")
> +	(plus:GPI (mult:GPI (match_dup 1) (match_dup 2))
> +		  (match_dup 3)))]
> +  ""
> +  "adds\\t%<w>0, %<w>3, %<w>1, lsl %p2"
> +  [(set_attr "v8type" "alu_shift")

alus_shift

> +;; zero_extend version of above
> +(define_insn "*adds_mul_imm_si_uxtw"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +	(compare:CC_NZ
> +	 (plus:SI (mult:SI
> +		   (match_operand:SI 1 "register_operand" "r")
> +		   (match_operand:QI 2 "aarch64_pwr_2_si" "n"))
> +		  (match_operand:SI 3 "register_operand" "rk"))
> +	 (const_int 0)))
> +   (set (match_operand:DI 0 "register_operand" "=r")
> +	(zero_extend:DI (plus:SI (mult:SI (match_dup 1) (match_dup 2))
> +				 (match_dup 3))))]
> +  ""
> +  "adds\\t%w0, %w3, %w1, lsl %p2"
> +  [(set_attr "v8type" "alu_shift")
> +   (set_attr "mode" "SI")]

alus_shift

Does this one have test coverage?

> +
> +(define_insn "*subs_<shift>_<mode>"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +	(compare:CC_NZ
> +	 (minus:GPI (match_operand:GPI 1 "register_operand" "r")
> +		    (ASHIFT:GPI
> +		     (match_operand:GPI 2 "register_operand" "r")
> +		     (match_operand:QI 3 "aarch64_shift_imm_<mode>" "n")))
> +	 (const_int 0)))
> +   (set (match_operand:GPI 0 "register_operand" "=r")
> +	(minus:GPI (match_dup 1)
> +		   (ASHIFT:GPI (match_dup 2) (match_dup 3))))]
> +  ""
> +  "subs\\t%<w>0, %<w>1, %<w>2, <shift> %3"
> +  [(set_attr "v8type" "alu_shift")

alus_shift

Does this one have test coverage?

> +   (set_attr "mode" "<MODE>")]
> +)
> +
> +;; zero_extend version of above
> +(define_insn "*subs_<shift>_si_uxtw"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +	(compare:CC_NZ
> +	 (minus:SI (match_operand:SI 1 "register_operand" "r")
> +		   (ASHIFT:SI
> +		    (match_operand:SI 2 "register_operand" "r")
> +		    (match_operand:QI 3 "aarch64_shift_imm_si" "n")))
> +	(const_int 0)))
> +   (set (match_operand:DI 0 "register_operand" "=r")
> +	(zero_extend:DI (minus:SI (match_dup 1)
> +				  (ASHIFT:SI (match_dup 2) (match_dup 3)))))]
> +  ""
> +  "subs\\t%w0, %w1, %w2, <shift> %3"
> +  [(set_attr "v8type" "alu_shift")

alus_shift
Does this one have test coverage?

> +   (set_attr "mode" "SI")]
> +)
> +
> +(define_insn "*subs_mul_imm_<mode>"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +	(compare:CC_NZ
> +	 (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
> +		    (mult:GPI
> +		     (match_operand:GPI 2 "register_operand" "r")
> +		     (match_operand:QI 3 "aarch64_pwr_2_<mode>" "n")))
> +	 (const_int 0)))
> +   (set (match_operand:GPI 0 "register_operand" "=r")
> +	(minus:GPI (match_dup 1)
> +		   (mult:GPI (match_dup 2) (match_dup 3))))]
> +  ""
> +  "subs\\t%<w>0, %<w>1, %<w>2, lsl %p3"
> +  [(set_attr "v8type" "alu_shift")

alus_shift

> +   (set_attr "mode" "<MODE>")]
> +)
> +
> +;; zero_extend version of above
> +(define_insn "*subs_mul_imm_si_uxtw"
> +  [(set (reg:CC_NZ CC_REGNUM)
> +	(compare:CC_NZ
> +	 (minus:SI (match_operand:SI 1 "register_operand" "rk")
> +		   (mult:SI
> +		    (match_operand:SI 2 "register_operand" "r")
> +		    (match_operand:QI 3 "aarch64_pwr_2_si" "n")))
> +	 (const_int 0)))
> +   (set (match_operand:DI 0 "register_operand" "=r")
> +	(zero_extend:DI (minus:SI (match_dup 1)
> +				  (mult:SI (match_dup 2) (match_dup 3)))))]
> +  ""
> +  "subs\\t%w0, %w1, %w2, lsl %p3"
> +  [(set_attr "v8type" "alu_shift")
> +   (set_attr "mode" "SI")]

alus_shift
Does this one have test coverage?

> +)
> +
>   (define_insn "*add<mode>3nr_compare0"
>     [(set (reg:CC_NZ CC_REGNUM)
>   	(compare:CC_NZ
> @@ -1633,7 +1773,7 @@
>
>   (define_insn "*sub<mode>3_compare0"
>     [(set (reg:CC_NZ CC_REGNUM)
> -	(compare:CC_NZ (minus:GPI (match_operand:GPI 1 "register_operand" "r")
> +	(compare:CC_NZ (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
>   				  (match_operand:GPI 2 "register_operand" "r"))

subs shifted register does not permit SP.

>   		       (const_int 0)))
>      (set (match_operand:GPI 0 "register_operand" "=r")
> @@ -1647,7 +1787,7 @@
>   ;; zero_extend version of above
>   (define_insn "*subsi3_compare0_uxtw"
>     [(set (reg:CC_NZ CC_REGNUM)
> -	(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "r")
> +	(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "rk")
>   				 (match_operand:SI 2 "register_operand" "r"))

Likewise.


Cheers
/Marcus

Patch

--- gcc/config/aarch64/aarch64.md	2013-03-26 12:51:12.180448029 +0530
+++ gcc/config/aarch64/aarch64.md	2013-03-26 16:48:37.256931141 +0530
@@ -1256,7 +1256,7 @@ 
 (define_insn "*add<mode>3_compare0"
   [(set (reg:CC_NZ CC_REGNUM)
 	(compare:CC_NZ
-	 (plus:GPI (match_operand:GPI 1 "register_operand" "%r,r")
+	 (plus:GPI (match_operand:GPI 1 "register_operand" "%rk,rk")
 		   (match_operand:GPI 2 "aarch64_plus_operand" "rI,J"))
 	 (const_int 0)))
    (set (match_operand:GPI 0 "register_operand" "=r,r")
@@ -1273,7 +1273,7 @@ 
 (define_insn "*addsi3_compare0_uxtw"
   [(set (reg:CC_NZ CC_REGNUM)
 	(compare:CC_NZ
-	 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
+	 (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk")
 		  (match_operand:SI 2 "aarch64_plus_operand" "rI,J"))
 	 (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r,r")
@@ -1286,6 +1286,146 @@ 
    (set_attr "mode" "SI")]
 )
 
+(define_insn "*adds_<shift>_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (plus:GPI (ASHIFT:GPI
+		    (match_operand:GPI 1 "register_operand" "r")
+		    (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
+		   (match_operand:GPI 3 "register_operand" "r"))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+	(plus:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))
+		  (match_dup 3)))]
+  ""
+  "adds\\t%<w>0, %<w>3, %<w>1, <shift> %2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*adds_<shift>_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (plus:SI (ASHIFT:SI
+		   (match_operand:SI 1 "register_operand" "r")
+		   (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
+		  (match_operand:SI 3 "register_operand" "r"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (plus:SI (ASHIFT:SI (match_dup 1) (match_dup 2))
+				 (match_dup 3))))]
+  ""
+  "adds\\t%w0, %w3, %w1, <shift> %2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*adds_mul_imm_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (plus:GPI (mult:GPI
+		    (match_operand:GPI 1 "register_operand" "r")
+		    (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))
+		   (match_operand:GPI 3 "register_operand" "rk"))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+	(plus:GPI (mult:GPI (match_dup 1) (match_dup 2))
+		  (match_dup 3)))]
+  ""
+  "adds\\t%<w>0, %<w>3, %<w>1, lsl %p2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*adds_mul_imm_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (plus:SI (mult:SI
+		   (match_operand:SI 1 "register_operand" "r")
+		   (match_operand:QI 2 "aarch64_pwr_2_si" "n"))
+		  (match_operand:SI 3 "register_operand" "rk"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (plus:SI (mult:SI (match_dup 1) (match_dup 2))
+				 (match_dup 3))))]
+  ""
+  "adds\\t%w0, %w3, %w1, lsl %p2"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*subs_<shift>_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (minus:GPI (match_operand:GPI 1 "register_operand" "r")
+		    (ASHIFT:GPI
+		     (match_operand:GPI 2 "register_operand" "r")
+		     (match_operand:QI 3 "aarch64_shift_imm_<mode>" "n")))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+	(minus:GPI (match_dup 1)
+		   (ASHIFT:GPI (match_dup 2) (match_dup 3))))]
+  ""
+  "subs\\t%<w>0, %<w>1, %<w>2, <shift> %3"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*subs_<shift>_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (minus:SI (match_operand:SI 1 "register_operand" "r")
+		   (ASHIFT:SI
+		    (match_operand:SI 2 "register_operand" "r")
+		    (match_operand:QI 3 "aarch64_shift_imm_si" "n")))
+	(const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (minus:SI (match_dup 1)
+				  (ASHIFT:SI (match_dup 2) (match_dup 3)))))]
+  ""
+  "subs\\t%w0, %w1, %w2, <shift> %3"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]
+)
+
+(define_insn "*subs_mul_imm_<mode>"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
+		    (mult:GPI
+		     (match_operand:GPI 2 "register_operand" "r")
+		     (match_operand:QI 3 "aarch64_pwr_2_<mode>" "n")))
+	 (const_int 0)))
+   (set (match_operand:GPI 0 "register_operand" "=r")
+	(minus:GPI (match_dup 1)
+		   (mult:GPI (match_dup 2) (match_dup 3))))]
+  ""
+  "subs\\t%<w>0, %<w>1, %<w>2, lsl %p3"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "<MODE>")]
+)
+
+;; zero_extend version of above
+(define_insn "*subs_mul_imm_si_uxtw"
+  [(set (reg:CC_NZ CC_REGNUM)
+	(compare:CC_NZ
+	 (minus:SI (match_operand:SI 1 "register_operand" "rk")
+		   (mult:SI
+		    (match_operand:SI 2 "register_operand" "r")
+		    (match_operand:QI 3 "aarch64_pwr_2_si" "n")))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (minus:SI (match_dup 1)
+				  (mult:SI (match_dup 2) (match_dup 3)))))]
+  ""
+  "subs\\t%w0, %w1, %w2, lsl %p3"
+  [(set_attr "v8type" "alu_shift")
+   (set_attr "mode" "SI")]
+)
+
 (define_insn "*add<mode>3nr_compare0"
   [(set (reg:CC_NZ CC_REGNUM)
 	(compare:CC_NZ
@@ -1633,7 +1773,7 @@ 
 
 (define_insn "*sub<mode>3_compare0"
   [(set (reg:CC_NZ CC_REGNUM)
-	(compare:CC_NZ (minus:GPI (match_operand:GPI 1 "register_operand" "r")
+	(compare:CC_NZ (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
 				  (match_operand:GPI 2 "register_operand" "r"))
 		       (const_int 0)))
    (set (match_operand:GPI 0 "register_operand" "=r")
@@ -1647,7 +1787,7 @@ 
 ;; zero_extend version of above
 (define_insn "*subsi3_compare0_uxtw"
   [(set (reg:CC_NZ CC_REGNUM)
-	(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "r")
+	(compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "rk")
 				 (match_operand:SI 2 "register_operand" "r"))
 		       (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
--- gcc/testsuite/gcc.target/aarch64/adds1.c	1970-01-01 05:30:00.000000000 +0530
+++ gcc/testsuite/gcc.target/aarch64/adds1.c	2013-03-26 16:47:38.760929157 +0530
@@ -0,0 +1,149 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+adds_si_test1 (int a, int b, int c)
+{
+  int d = a + b;
+
+  /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+adds_si_test2 (int a, int b, int c)
+{
+  int d = a + 0xff;
+
+  /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, 255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+adds_si_test3 (int a, int b, int c)
+{
+  int d = a + (b << 3);
+
+  /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+adds_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + b;
+
+  /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+adds_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + 0xff;
+
+  /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, 255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+adds_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + (b << 3);
+
+  /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = adds_si_test1 (29, 4, 5);
+  if (x != 42)
+    abort ();
+
+  x = adds_si_test1 (5, 2, 20);
+  if (x != 29)
+    abort ();
+
+  x = adds_si_test2 (29, 4, 5);
+  if (x != 293)
+    abort ();
+
+  x = adds_si_test2 (1024, 2, 20);
+  if (x != 1301)
+    abort ();
+
+  x = adds_si_test3 (35, 4, 5);
+  if (x != 76)
+    abort ();
+
+  x = adds_si_test3 (5, 2, 20);
+  if (x != 43)
+    abort ();
+
+  y = adds_di_test1 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+
+  if (y != 0xc75050536)
+    abort ();
+
+  y = adds_di_test1 (0x5000500050005ll,
+		     0x2111211121112ll,
+		     0x0000000002020ll);
+  if (y != 0x9222922294249)
+    abort ();
+
+  y = adds_di_test2 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955050631)
+    abort ();
+
+  y = adds_di_test2 (0x130002900ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955052f08)
+    abort ();
+
+  y = adds_di_test3 (0x130000029ll,
+		     0x064000008ll,
+		     0x505050505ll);
+  if (y != 0x9b9050576)
+    abort ();
+
+  y = adds_di_test3 (0x130002900ll,
+		     0x088000008ll,
+		     0x505050505ll);
+  if (y != 0xafd052e4d)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
--- gcc/testsuite/gcc.target/aarch64/adds2.c	1970-01-01 05:30:00.000000000 +0530
+++ gcc/testsuite/gcc.target/aarch64/adds2.c	2013-03-26 16:47:38.832929159 +0530
@@ -0,0 +1,155 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+adds_si_test1 (int a, int b, int c)
+{
+  int d = a + b;
+
+  /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+adds_si_test2 (int a, int b, int c)
+{
+  int d = a + 0xfff;
+
+  /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, 4095" } } */
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, 4095" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+adds_si_test3 (int a, int b, int c)
+{
+  int d = a + (b << 3);
+
+  /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+adds_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + b;
+
+  /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+adds_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + 0x1000ll;
+
+  /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, 4096" } } */
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, 4096" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+adds_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + (b << 3);
+
+  /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = adds_si_test1 (29, 4, 5);
+  if (x != 42)
+    abort ();
+
+  x = adds_si_test1 (5, 2, 20);
+  if (x != 29)
+    abort ();
+
+  x = adds_si_test2 (29, 4, 5);
+  if (x != 4133)
+    abort ();
+
+  x = adds_si_test2 (1024, 2, 20);
+  if (x != 5141)
+    abort ();
+
+  x = adds_si_test3 (35, 4, 5);
+  if (x != 76)
+    abort ();
+
+  x = adds_si_test3 (5, 2, 20);
+  if (x != 43)
+    abort ();
+
+  y = adds_di_test1 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+
+  if (y != 0xc75050536)
+    abort ();
+
+  y = adds_di_test1 (0x5000500050005ll,
+		     0x2111211121112ll,
+		     0x0000000002020ll);
+  if (y != 0x9222922294249)
+    abort ();
+
+  y = adds_di_test2 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955051532)
+    abort ();
+
+  y = adds_di_test2 (0x540004100ll,
+		     0x320000004ll,
+		     0x805050205ll);
+  if (y != 0x1065055309)
+    abort ();
+
+  y = adds_di_test3 (0x130000029ll,
+		     0x064000008ll,
+		     0x505050505ll);
+  if (y != 0x9b9050576)
+    abort ();
+
+  y = adds_di_test3 (0x130002900ll,
+		     0x088000008ll,
+		     0x505050505ll);
+  if (y != 0xafd052e4d)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
--- gcc/testsuite/gcc.target/aarch64/subs1.c	1970-01-01 05:30:00.000000000 +0530
+++ gcc/testsuite/gcc.target/aarch64/subs1.c	2013-03-26 16:47:43.164929306 +0530
@@ -0,0 +1,149 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+subs_si_test1 (int a, int b, int c)
+{
+  int d = a - c;
+
+  /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+subs_si_test2 (int a, int b, int c)
+{
+  int d = a - 0xff;
+
+  /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, #255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+subs_si_test3 (int a, int b, int c)
+{
+  int d = a - (b << 3);
+
+  /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+subs_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - c;
+
+  /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+subs_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - 0xff;
+
+  /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, #255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+subs_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - (b << 3);
+
+  /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = subs_si_test1 (29, 4, 5);
+  if (x != 33)
+    abort ();
+
+  x = subs_si_test1 (5, 2, 20);
+  if (x != 7)
+    abort ();
+
+  x = subs_si_test2 (29, 4, 5);
+  if (x != -217)
+    abort ();
+
+  x = subs_si_test2 (1024, 2, 20);
+  if (x != 791)
+    abort ();
+
+  x = subs_si_test3 (35, 4, 5);
+  if (x != 12)
+    abort ();
+
+  x = subs_si_test3 (5, 2, 20);
+  if (x != 11)
+    abort ();
+
+  y = subs_di_test1 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+
+  if (y != 0x45000002d)
+    abort ();
+
+  y = subs_di_test1 (0x5000500050005ll,
+		     0x2111211121112ll,
+		     0x0000000002020ll);
+  if (y != 0x7111711171117)
+    abort ();
+
+  y = subs_di_test2 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955050433)
+    abort ();
+
+  y = subs_di_test2 (0x130002900ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955052d0a)
+    abort ();
+
+  y = subs_di_test3 (0x130000029ll,
+		     0x064000008ll,
+		     0x505050505ll);
+  if (y != 0x3790504f6)
+    abort ();
+
+  y = subs_di_test3 (0x130002900ll,
+		     0x088000008ll,
+		     0x505050505ll);
+  if (y != 0x27d052dcd)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
--- gcc/testsuite/gcc.target/aarch64/subs2.c	1970-01-01 05:30:00.000000000 +0530
+++ gcc/testsuite/gcc.target/aarch64/subs2.c	2013-03-26 16:47:44.556929354 +0530
@@ -0,0 +1,155 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+int
+subs_si_test1 (int a, int b, int c)
+{
+  int d = a - b;
+
+  /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+subs_si_test2 (int a, int b, int c)
+{
+  int d = a - 0xfff;
+
+  /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, #4095" } } */
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, #4095" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+subs_si_test3 (int a, int b, int c)
+{
+  int d = a - (b << 3);
+
+  /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+subs_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - b;
+
+  /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+subs_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - 0x1000ll;
+
+  /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, #4096" } } */
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, #4096" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+subs_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - (b << 3);
+
+  /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = subs_si_test1 (29, 4, 5);
+  if (x != 34)
+    abort ();
+
+  x = subs_si_test1 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  x = subs_si_test2 (29, 4, 5);
+  if (x != 34)
+    abort ();
+
+  x = subs_si_test2 (1024, 2, 20);
+  if (x != 1044)
+    abort ();
+
+  x = subs_si_test3 (35, 4, 5);
+  if (x != 12)
+    abort ();
+
+  x = subs_si_test3 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  y = subs_di_test1 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+
+  if (y != 0x63505052e)
+    abort ();
+
+  y = subs_di_test1 (0x5000500050005ll,
+		     0x2111211121112ll,
+		     0x0000000002020ll);
+  if (y != 0x5000500052025)
+    abort ();
+
+  y = subs_di_test2 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x95504f532)
+    abort ();
+
+  y = subs_di_test2 (0x540004100ll,
+		     0x320000004ll,
+		     0x805050205ll);
+  if (y != 0x1065053309)
+    abort ();
+
+  y = subs_di_test3 (0x130000029ll,
+		     0x064000008ll,
+		     0x505050505ll);
+  if (y != 0x63505052e)
+    abort ();
+
+  y = subs_di_test3 (0x130002900ll,
+		     0x088000008ll,
+		     0x505050505ll);
+  if (y != 0x635052e05)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */