From patchwork Tue Mar 26 06:55:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Walter Lee X-Patchwork-Id: 231098 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 7ECCF2C00C6 for ; Tue, 26 Mar 2013 17:55:50 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:reply-to:mime-version:content-type; q=dns; s=default; b=ZfNrMDUJ9zAjcif8eGC1e/dR96DePEXeuTFkG9G7fI+ 63U/Q9Fa5wVW84YzIuczG5SUT0kF3NZarlUyTjOaqp5mVkq7xE5z35qTVgViYSgF Mnhdc9Ebi4XArjSwQVS4mhhLITuKcTFH/MzabbtZalWx1/QURjmbny79FmwCfnTQ = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:reply-to:mime-version:content-type; s=default; bh=P/nGIIuEtkYpdsfI9M6VHqTpotA=; b=CAIPGjgvNMT3ECGVs PGtitHr6avYgZLUu5GdEi9sWzZXylhxRyJgvO+RWKJDM+Hquv8r2zz2DQJb/dg9c JuLfLZp83d5fPnfEhxaxO92cUIY6PFqfdhiy8aThR/FTnRiZt1UrGq/lxT7iYpC8 a6NHhKftuYqd9GL6/O6IM2fLAg= Received: (qmail 31676 invoked by alias); 26 Mar 2013 06:55:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 31661 invoked by uid 89); 26 Mar 2013 06:55:33 -0000 X-Spam-SWARE-Status: No, score=-2.7 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.1 Received: from usmamail.tilera.com (HELO USMAMAIL.TILERA.COM) (12.216.194.151) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 26 Mar 2013 06:55:30 +0000 Received: from farm-0001.internal.tilera.com (10.2.0.31) by USMAEXCH2.tad.internal.tilera.com (10.3.0.33) with Microsoft SMTP Server (TLS) id 14.0.722.0; Tue, 26 Mar 2013 02:55:28 -0400 Received: (from walt@localhost) by farm-0001.internal.tilera.com (8.14.4/8.12.11/Submit) id r2Q6tSiT017301; Tue, 26 Mar 2013 02:55:28 -0400 Date: Tue, 26 Mar 2013 02:55:28 -0400 Message-ID: <201303260655.r2Q6tSiT017301@farm-0001.internal.tilera.com> From: Walter Lee To: Subject: [committed] TILE-Gx: add float conversion patterns. Reply-To: Walter Lee MIME-Version: 1.0 This patch adds patterns for floatsisf2, floatunssisf2, floatsidf2, and floatunssidf2. * config/tilegx/tilegx.md (floatsisf2): New pattern. (floatunssisf2): New pattern. (floatsidf2): New pattern. (floatunssidf2): New pattern. Index: gcc/config/tilegx/tilegx.md =================================================================== --- gcc/config/tilegx/tilegx.md (revision 197072) +++ gcc/config/tilegx/tilegx.md (working copy) @@ -2129,6 +2129,108 @@ "" "rotl\t%0, %r1, %r2") +;; Integer to floating point conversions + +(define_expand "floatsisf2" + [(set (match_operand:SF 0 "register_operand" "") + (float:SI (match_operand:SI 1 "register_operand" "")))] + "" +{ + rtx result = gen_lowpart (DImode, operands[0]); + rtx a = operands[1]; + + rtx nega = gen_reg_rtx (SImode); + rtx exp = gen_reg_rtx (DImode); + rtx sign = gen_reg_rtx (DImode); + rtx abs = gen_reg_rtx (DImode); + rtx flags = gen_reg_rtx (DImode); + rtx tmp1 = gen_reg_rtx (DImode); + rtx tmp2 = gen_reg_rtx (DImode); + + emit_move_insn (exp, GEN_INT (0x9e)); + + emit_insn (gen_negsi2 (nega, a)); + + emit_insn (gen_insn_cmplts_sisi (gen_lowpart (SImode, sign), a, const0_rtx)); + emit_insn (gen_insn_cmoveqz (abs, gen_lowpart (DImode, nega), sign, + gen_lowpart (DImode, a))); + + emit_insn (gen_insn_bfins (tmp1, exp, sign, GEN_INT (10), GEN_INT (10))); + emit_insn (gen_insn_bfins (tmp2, tmp1, abs, GEN_INT (32), GEN_INT (63))); + emit_insn (gen_insn_fsingle_pack1 (flags, tmp2)); + emit_insn (gen_insn_fsingle_pack2 (result, tmp2, flags)); + DONE; +}) + +(define_expand "floatunssisf2" + [(set (match_operand:SF 0 "register_operand" "") + (float:SI (match_operand:SI 1 "register_operand" "")))] + "" +{ + rtx result = gen_lowpart (DImode, operands[0]); + rtx a = operands[1]; + + rtx exp = gen_reg_rtx (DImode); + rtx flags = gen_reg_rtx (DImode); + rtx tmp = gen_reg_rtx (DImode); + + emit_move_insn (exp, GEN_INT (0x9e)); + emit_insn (gen_insn_bfins (tmp, exp, gen_lowpart (DImode, a), + GEN_INT (32), GEN_INT (63))); + emit_insn (gen_insn_fsingle_pack1 (flags, tmp)); + emit_insn (gen_insn_fsingle_pack2 (result, tmp, flags)); + DONE; +}) + +(define_expand "floatsidf2" + [(set (match_operand:DF 0 "register_operand" "") + (float:SI (match_operand:SI 1 "register_operand" "")))] + "" +{ + rtx result = gen_lowpart (DImode, operands[0]); + rtx a = gen_lowpart (DImode, operands[1]); + + rtx nega = gen_reg_rtx (DImode); + rtx exp = gen_reg_rtx (DImode); + rtx sign = gen_reg_rtx (DImode); + rtx abs = gen_reg_rtx (DImode); + rtx tmp1 = gen_reg_rtx (DImode); + rtx tmp2 = gen_reg_rtx (DImode); + rtx tmp3 = gen_reg_rtx (DImode); + + emit_move_insn (exp, GEN_INT (0x21b00)); + + emit_insn (gen_negdi2 (nega, a)); + + emit_insn (gen_insn_cmplts_didi (sign, a, const0_rtx)); + emit_insn (gen_insn_cmovnez (abs, a, sign, nega)); + + emit_insn (gen_ashldi3 (tmp1, abs, GEN_INT (4))); + emit_insn (gen_insn_bfins (tmp2, exp, sign, GEN_INT (20), GEN_INT (20))); + emit_insn (gen_insn_fdouble_pack1 (tmp3, tmp1, tmp2)); + emit_insn (gen_insn_fdouble_pack2 (result, tmp3, tmp1, const0_rtx)); + DONE; +}) + +(define_expand "floatunssidf2" + [(set (match_operand:DF 0 "register_operand" "") + (float:SI (match_operand:SI 1 "register_operand" "")))] + "" +{ + rtx result = gen_lowpart (DImode, operands[0]); + rtx a = gen_lowpart (DImode, operands[1]); + + rtx exp = gen_reg_rtx (DImode); + rtx tmp1 = gen_reg_rtx (DImode); + rtx tmp2 = gen_reg_rtx (DImode); + + emit_move_insn (exp, GEN_INT (0x21b00)); + emit_insn (gen_insn_bfins (tmp1, const0_rtx, a, GEN_INT (4), GEN_INT (35))); + emit_insn (gen_insn_fdouble_pack1 (tmp2, tmp1, exp)); + emit_insn (gen_insn_fdouble_pack2 (result, tmp2, tmp1, const0_rtx)); + DONE; +}) + ;; ;; Multiplies