From patchwork Mon Mar 25 22:50:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Ellcey X-Patchwork-Id: 231007 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 479552C00BC for ; Tue, 26 Mar 2013 09:50:32 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:content-transfer-encoding; q=dns; s= default; b=CyIHe4ZPJQzemzA7+MP7zmW/exUqiJopwXNzgTPoNf5dnKwzQ22DB rHQWklU3CUDcOylKHeZrlxeT6+cgT68ftJBdWLo3p+j472CtsThU5E5WAAFG/nLF XuyXzdBYMrq8RV9a12jv7ALzGUkpDPU3OSuexKGB1uk/KFoLWMF6fg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:content-transfer-encoding; s=default; bh=hXpRTugd69/vYLT1cYjJ0ZWaRpQ=; b=kREdDR9JYxBEHjoqRXBPZiG1pqqf 9GoGeE9O3n+GJHp84f6xnZsdMBJW+IqeqU+t6HGJ+51PuSWlSZZu8t/O1rPgN+Xw 31H0lP/yD5eyNzen/1iNCTPJPLTpjcO+SfNJuUhDviykaNbq8b1FrlWbBHem/BCQ kpyIkxH2rFjfgvk= Received: (qmail 11814 invoked by alias); 25 Mar 2013 22:50:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 11787 invoked by uid 89); 25 Mar 2013 22:50:11 -0000 Received: from multi.imgtec.com (HELO multi.imgtec.com) (194.200.65.239) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Mon, 25 Mar 2013 22:50:11 +0000 Subject: Re: [patch, mips] Patch to control the use of integer madd/msub instructions From: Steve Ellcey To: Richard Sandiford CC: In-Reply-To: <87txnzup2b.fsf@talisman.default> References: <200323ec-7686-44f6-a5de-edc726909141@BAMAIL02.ba.imgtec.org> <87hak241ce.fsf@talisman.default> <1364227928.18314.120.camel@ubuntu-sellcey> <87li9bv35q.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> <1364244812.18314.128.camel@ubuntu-sellcey> <87txnzup2b.fsf@talisman.default> Date: Mon, 25 Mar 2013 15:50:06 -0700 Message-ID: <1364251806.18314.133.camel@ubuntu-sellcey> MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01181__2013_03_25_22_50_09 On Mon, 2013-03-25 at 21:50 +0000, Richard Sandiford wrote: > That's trivial enough not to need a retest, but please post the > invoke.texi patch. > > Thanks, > Richard Ah, yes I always forget the documentation. Here is the complete patch. It has the invoke.texi change at the bottom and I fixed up the comments in mips.h. Steve Ellcey sellcey@imgtec.com 2013-03-25 Steve Ellcey * config/mips/mmips-cpus.def (74kc, 74kf2_1, 74kf, 74kf, 74kf1_1, 74kfx, 74kx, 74kf3_2): Add PTF_AVOID_IMADD. * config/mips/mips.c (mips_option_override): Set IMADD default. * config/mips/mips.h (PTF_AVOID_IMADD): New. (ISA_HAS_MADD_MSUB): Remove MIPS16 check. (GENERATE_MADD_MSUB): Remove TUNE_74K check, add MIPS16 check. * config/mips/mips.md (mimadd): New flag for integer madd/msub. * doc/invoke.texi (-mimadd/-mno-imadd): New. diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 1cc1999..9e5fd16 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -121,13 +121,13 @@ MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, 33, 0) MIPS_CPU ("34kx", PROCESSOR_24KF1_1, 33, 0) MIPS_CPU ("34kn", PROCESSOR_24KC, 33, 0) /* 34K with MT but no DSP. */ -MIPS_CPU ("74kc", PROCESSOR_74KC, 33, 0) /* 74K with DSPr2. */ -MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, 0) -MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, 0) -MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, 0) -MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, 0) -MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, 0) -MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, 0) +MIPS_CPU ("74kc", PROCESSOR_74KC, 33, PTF_AVOID_IMADD) /* 74K with DSPr2. */ +MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, PTF_AVOID_IMADD) MIPS_CPU ("1004kc", PROCESSOR_24KC, 33, 0) /* 1004K with MT/DSP. */ MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e4ab271..e3469da 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -16862,6 +16862,21 @@ mips_option_override (void) warning (0, "the %qs architecture does not support branch-likely" " instructions", mips_arch_info->name); + /* If the user hasn't specified -mimadd or -mno-imadd set + MASK_IMADD based on the target architecture and tuning + flags. */ + if ((target_flags_explicit & MASK_IMADD) == 0) + { + if (ISA_HAS_MADD_MSUB && + (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0) + target_flags |= MASK_IMADD; + else + target_flags &= ~MASK_IMADD; + } + else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB) + warning (0, "the %qs architecture does not support madd or msub" + " instructions", mips_arch_info->name); + /* The effect of -mabicalls isn't defined for the EABI. */ if (mips_abi == ABI_EABI && TARGET_ABICALLS) { diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 0db3698..dd694f3 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -47,8 +47,15 @@ extern int target_flags_explicit; PTF_AVOID_BRANCHLIKELY Set if it is usually not profitable to use branch-likely instructions for this target, typically because the branches are always predicted - taken and so incur a large overhead when not taken. */ -#define PTF_AVOID_BRANCHLIKELY 0x1 + taken and so incur a large overhead when not taken. + + PTF_AVOID_IMADD + Set if it is usually not profitable to use the integer MADD or MSUB + instructions because of the overhead of getting the result out of + the HI/LO registers. */ + +#define PTF_AVOID_BRANCHLIKELY 0x1 +#define PTF_AVOID_IMADD 0x2 /* Information about one recognized processor. Defined here for the benefit of TARGET_CPU_CPP_BUILTINS. */ @@ -874,14 +881,13 @@ struct mips_cpu_info { && !TARGET_MIPS16) /* ISA has integer multiply-accumulate instructions, madd and msub. */ -#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ - || ISA_MIPS32R2 \ - || ISA_MIPS64 \ - || ISA_MIPS64R2) \ - && !TARGET_MIPS16) +#define ISA_HAS_MADD_MSUB (ISA_MIPS32 \ + || ISA_MIPS32R2 \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) /* Integer multiply-accumulate instructions should be generated. */ -#define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K) +#define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index f9e88b3..e11710d 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -58,6 +58,10 @@ mmad Target Report Var(TARGET_MAD) Use PMC-style 'mad' instructions +mimadd +Target Report Mask(IMADD) +Use integer madd/msub instructions + march= Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value) -march=ISA Generate code for the given ISA diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9b8b36a..3054e5c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -766,7 +766,7 @@ Objective-C and Objective-C++ Dialects}. -mcheck-zero-division -mno-check-zero-division @gol -mdivide-traps -mdivide-breaks @gol -mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol --mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol +-mmad -mno-mad -mimadd -mno-imadd -mfused-madd -mno-fused-madd -nocpp @gol -mfix-24k -mno-fix-24k @gol -mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol -mfix-r10000 -mno-fix-r10000 -mfix-vr4120 -mno-fix-vr4120 @gol @@ -16481,6 +16481,15 @@ This option has no effect on abicalls code. The default is Enable (disable) use of the @code{mad}, @code{madu} and @code{mul} instructions, as provided by the R4650 ISA@. +@item -mimadd +@itemx -mno-imadd +@opindex mimadd +@opindex mno-imadd +Enable (disable) use of the @code{madd} and @code{msub} integer +instructions. The default is @option{-mimadd} on architectures +that support @code{madd} and @code{msub} except for the 74k +architecture where it was found to generate slower code. + @item -mfused-madd @itemx -mno-fused-madd @opindex mfused-madd