From patchwork Mon Mar 25 20:53:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Ellcey X-Patchwork-Id: 230987 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 068DC2C009D for ; Tue, 26 Mar 2013 07:54:05 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:content-transfer-encoding; q=dns; s= default; b=u49zkHpO2fSObSl/Ywi9SKV8j5s7M9DpBvjGXVxOldzGEXR6pKnJt SV7mVv9Kimy/wKpuWc00/n6/utEAOwDW2xqnGU/uWjLHhNKvqajrLPQU6gqMF3Qg PfF7LTsgzlqfhrIPKY0HSPPjRU5kyt53wB/99biNrgvzF8Acz6Ja6s= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:content-transfer-encoding; s=default; bh=DMxfiFm0E1NuE9wEDNXhV3v7knE=; b=WDiA5dmlbICMQWx6jlmCi3xx3heb m+gD0qvS3Hzq5U00yibyBbL0huxD6jfzAvLP/saU2WF/KqEkCtYAS4Lohmkf8NiE DTY1bgesMU3aqXT0gJk1kHiOWEflxIznIw400t8NDqmy49DpdAM6m50jCKXlp2QG 7XX06lzjAya6Je4= Received: (qmail 9756 invoked by alias); 25 Mar 2013 20:53:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9598 invoked by uid 89); 25 Mar 2013 20:53:41 -0000 Received: from multi.imgtec.com (HELO multi.imgtec.com) (194.200.65.239) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Mon, 25 Mar 2013 20:53:41 +0000 Subject: Re: [patch, mips] Patch to control the use of integer madd/msub instructions From: Steve Ellcey To: Richard Sandiford CC: In-Reply-To: <87li9bv35q.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> References: <200323ec-7686-44f6-a5de-edc726909141@BAMAIL02.ba.imgtec.org> <87hak241ce.fsf@talisman.default> <1364227928.18314.120.camel@ubuntu-sellcey> <87li9bv35q.fsf@sandifor-thinkpad.stglab.manchester.uk.ibm.com> Date: Mon, 25 Mar 2013 13:53:32 -0700 Message-ID: <1364244812.18314.128.camel@ubuntu-sellcey> MIME-Version: 1.0 X-SEF-Processed: 7_3_0_01181__2013_03_25_20_53_35 On Mon, 2013-03-25 at 16:45 +0000, Richard Sandiford wrote: > -mllsc is a little different in that it can be used even when the > ISA doesn't support it (thanks to kernel emulation). -mimadd isn't > like that though: we only want to use MADD/MSUB if the ISA has it. > So I think it makes sense to leave -mllsc as it is but do -mimadd > in the same way as -mbranch-likely. > > Thanks, > Richard OK, Here is a patch that implements -mimadd in the same manner as -mbranch-likely. Steve Ellcey sellcey@imgtec.com 2013-03-25 Steve Ellcey * config/mips/mmips-cpus.def (74kc, 74kf2_1, 74kf, 74kf, 74kf1_1, 74kfx, 74kx, 74kf3_2): Add PTF_AVOID_IMADD. * config/mips/mips.c (mips_option_override): Set IMADD default. * config/mips/mips.h (PTF_AVOID_IMADD): New. (ISA_HAS_MADD_MSUB): Remove MIPS16 check. (GENERATE_MADD_MSUB): Remove TUNE_74K check, add MIPS16 check. * config/mips/mips.md (mimadd): New flag for integer madd/msub. diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 93c305a..c920c73 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -119,13 +119,13 @@ MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, 33, 0) MIPS_CPU ("34kx", PROCESSOR_24KF1_1, 33, 0) MIPS_CPU ("34kn", PROCESSOR_24KC, 33, 0) /* 34K with MT but no DSP. */ -MIPS_CPU ("74kc", PROCESSOR_74KC, 33, 0) /* 74K with DSPr2. */ -MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, 0) -MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, 0) -MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, 0) -MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, 0) -MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, 0) -MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, 0) +MIPS_CPU ("74kc", PROCESSOR_74KC, 33, PTF_AVOID_IMADD) /* 74K with DSPr2. */ +MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) +MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, PTF_AVOID_IMADD) MIPS_CPU ("1004kc", PROCESSOR_24KC, 33, 0) /* 1004K with MT/DSP. */ MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 252e828..0aaf4c6 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -16607,6 +16607,21 @@ mips_option_override (void) warning (0, "the %qs architecture does not support branch-likely" " instructions", mips_arch_info->name); + /* If the user hasn't specified -mimadd or -mno-imadd set + MASK_IMADD based on the target architecture and tuning + flags. */ + if ((target_flags_explicit & MASK_IMADD) == 0) + { + if (ISA_HAS_MADD_MSUB && + (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0) + target_flags |= MASK_IMADD; + else + target_flags &= ~MASK_IMADD; + } + else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB) + warning (0, "the %qs architecture does not support madd or msub" + " instructions", mips_arch_info->name); + /* The effect of -mabicalls isn't defined for the EABI. */ if (mips_abi == ABI_EABI && TARGET_ABICALLS) { diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 0acce14..534ea26 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -42,13 +42,17 @@ extern int target_flags_explicit; #define ABI_EABI 3 #define ABI_O64 4 -/* Masks that affect tuning. - - PTF_AVOID_BRANCHLIKELY - Set if it is usually not profitable to use branch-likely instructions - for this target, typically because the branches are always predicted - taken and so incur a large overhead when not taken. */ -#define PTF_AVOID_BRANCHLIKELY 0x1 +/* Masks that affect tuning. */ + +/* Set PTF_AVOID_BRANCHLIKELY if is usually not profitable to use + branch-likely instructions for this target, typically because + the branches are always predicted taken and so incur a large + overhead when not taken. */ +#define PTF_AVOID_BRANCHLIKELY 0x1 +/* Set PTF_AVOID_IMADD if it is usually not profitable to use the + integer madd or msub instructions because of the overhead of + getting the result out of the HI/LO registers. */ +#define PTF_AVOID_IMADD 0x2 /* Information about one recognized processor. Defined here for the benefit of TARGET_CPU_CPP_BUILTINS. */ @@ -868,14 +872,13 @@ struct mips_cpu_info { && !TARGET_MIPS16) /* ISA has integer multiply-accumulate instructions, madd and msub. */ -#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ - || ISA_MIPS32R2 \ - || ISA_MIPS64 \ - || ISA_MIPS64R2) \ - && !TARGET_MIPS16) +#define ISA_HAS_MADD_MSUB (ISA_MIPS32 \ + || ISA_MIPS32R2 \ + || ISA_MIPS64 \ + || ISA_MIPS64R2) /* Integer multiply-accumulate instructions should be generated. */ -#define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K) +#define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index d8ef2e7..6b3024b 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -58,6 +58,10 @@ mmad Target Report Var(TARGET_MAD) Use PMC-style 'mad' instructions +mimadd +Target Report Mask(IMADD) +Use integer madd/msub instructions + march= Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value) -march=ISA Generate code for the given ISA