Patchwork [U-Boot,v2,batch,4,21/29] powerpc/b4860: fix for Serdes connectivity to SFP's

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Submitter York Sun
Date March 25, 2013, 5:40 p.m.
Message ID <1364233225-31262-21-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/230836/
State Accepted, archived
Delegated to: Andy Fleming
Headers show

Comments

York Sun - March 25, 2013, 5:40 p.m.
From: Shaveta Leekha <shaveta@freescale.com>

Crossbar switches were wrongly programmed to
route the CPRI lanes to SFP as the connectivity table
was not correct.
Modified it correctly for SFPs connections.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/fdt.c                   |    5 ++++
 board/freescale/b4860qds/b4860qds.c              |    6 +++--
 board/freescale/b4860qds/b4860qds_crossbar_con.h |   31 +++++++++++++++-------
 3 files changed, 30 insertions(+), 12 deletions(-)

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index c7ab146..c706b9b 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -665,6 +665,11 @@  void ft_cpu_setup(void *blob, bd_t *bd)
 		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2",
 			       "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+	do_fixup_by_compat_u32(blob, "fsl,mpic",
+			       "clock-frequency", get_bus_freq(0)/2, 1);
+#else
+	do_fixup_by_compat_u32(blob, "fsl,mpic",
+			       "clock-frequency", get_bus_freq(0), 1);
 #endif
 
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 41887c2..a39c17a 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -166,11 +166,13 @@  int configure_vsc3316_3308(void)
 		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
 		if (!ret) {
 			ret = vsc3316_config(VSC3316_TX_ADDRESS,
-					vsc16_tx_sgmii_lane_ab, num_vsc16_con);
+					vsc16_tx_4sfp_sgmii_12_56,
+					num_vsc16_con);
 			if (ret)
 				return ret;
 			ret = vsc3316_config(VSC3316_RX_ADDRESS,
-					vsc16_rx_sgmii_lane_ab, num_vsc16_con);
+					vsc16_rx_4sfp_sgmii_12_56,
+					num_vsc16_con);
 			if (ret)
 				return ret;
 		} else {
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index 994dec5..c2b6c44 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -26,42 +26,53 @@ 
 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
 				{5, 11}, {4, 5}, {2, 6}, {12, 9} };
 
-static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1},
-				{5, 15}, {4, 14}, {2, 12}, {12, 13} };
+static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+				{7, 8}, {9, 0}, {2, 14}, {12, 15},
+				{-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
+				{7, 8}, {9, 0}, {5, 14}, {4, 15},
+				{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
 static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
+
 static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
 			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
 				{11, 11}, {5, 10}, {6, 3}, {9, 12} };
 
-static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9},
+static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
 				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12},
-		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+				{7, 8}, {1, 9}, {14, 3}, {15, 12},
+				{-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
+				{7, 8}, {1, 9}, {14, 11}, {15, 10},
+				{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
 static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
-static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1},
+static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
 			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
 static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
 
-static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} };
+static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
 
 static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
 
-static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} };
+static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
 
 #endif