Patchwork [U-Boot,v2,batch,4,20/29] powerpc/doc: Fix the misalignment of document README.srio-pcie-boot-corenet

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Submitter York Sun
Date March 25, 2013, 5:40 p.m.
Message ID <1364233225-31262-20-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/230835/
State Superseded
Delegated to: Andy Fleming
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Comments

York Sun - March 25, 2013, 5:40 p.m.
From: Liu Gang <Gang.Liu@freescale.com>

Misalignment will be found in the doc/README.srio-pcie-boot-corenet
file when the tabs are set to 8 characters. And the standard for u-boot
should be 8 character tabs!

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
---
 doc/README.srio-pcie-boot-corenet |   12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Patch

diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet
index cd7e7ee..7e68174 100644
--- a/doc/README.srio-pcie-boot-corenet
+++ b/doc/README.srio-pcie-boot-corenet
@@ -21,13 +21,13 @@  Environment of the SRIO or PCIE boot:
 	e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
 	   the boot location to SRIO or PCIE, and holdoff all the cores.
 
-	----------        -----------             -----------
-	|		  |       |         |             |         |
-	|		  |       |         |             |         |
+	-----------       -----------             -----------
+	|         |       |         |             |         |
+	|         |       |         |             |         |
 	| NorFlash|<----->| Master  |SRIO or PCIE |  Slave  |<---->[EEPROM]
-	|		  |       |         |<===========>|         |
-	|		  |       |         |             |         |
-	----------        -----------             -----------
+	|         |       |         |<===========>|         |
+	|         |       |         |             |         |
+	-----------       -----------             -----------
 
 The example based on P4080DS platform:
 	Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.