Patchwork [U-Boot,v2,batch,4,18/29] powerpc/t4qds: Add SW7[4] in the DIP switch display

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Submitter York Sun
Date March 25, 2013, 5:40 p.m.
Message ID <1364233225-31262-18-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/230833/
State Accepted, archived
Delegated to: Andy Fleming
Headers show

Comments

York Sun - March 25, 2013, 5:40 p.m.
SW7[4] is the new bit which controls the mapping of eMMC vs SDHC.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 board/freescale/t4qds/t4qds.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Patch

diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index b48855e..f0f280b 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -801,7 +801,7 @@  void qixis_dump_switch(void)
 	 * Any bit with 1 means that bit cannot be reverse engineered.
 	 * It will be displayed as _ in binary format.
 	 */
-	static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f};
+	static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
 	char buf[10];
 	u8 brdcfg[16], dutcfg[16];
 
@@ -832,7 +832,8 @@  void qixis_dump_switch(void)
 	sw[5] = ((brdcfg[0] & 0x0f) << 4)	| \
 		((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
 		((brdcfg[0] & 0x40) >> 5);
-	sw[6] = (brdcfg[11] & 0x20);
+	sw[6] = (brdcfg[11] & 0x20)		|
+		((brdcfg[5] & 0x02) << 3);
 	sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
 		((brdcfg[5] & 0x10) << 2);
 	sw[8] = ((brdcfg[12] & 0x08) << 4)	| \