From patchwork Mon Mar 25 17:39:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 230820 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 616852C009B for ; Tue, 26 Mar 2013 04:42:06 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3FCA24A2DD; Mon, 25 Mar 2013 18:41:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vTPWuIaCZMyJ; Mon, 25 Mar 2013 18:41:26 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 03A4A4A29C; Mon, 25 Mar 2013 18:40:35 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DC3624A1B6 for ; Mon, 25 Mar 2013 18:40:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YbneIsajEHkL for ; Mon, 25 Mar 2013 18:40:24 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from va3outboundpool.messaging.microsoft.com (va3ehsobe003.messaging.microsoft.com [216.32.180.13]) by theia.denx.de (Postfix) with ESMTPS id E9AE94A1E3 for ; Mon, 25 Mar 2013 18:39:59 +0100 (CET) Received: from mail82-va3-R.bigfish.com (10.7.14.237) by VA3EHSOBE008.bigfish.com (10.7.40.28) with Microsoft SMTP Server id 14.1.225.23; Mon, 25 Mar 2013 17:39:58 +0000 Received: from mail82-va3 (localhost [127.0.0.1]) by mail82-va3-R.bigfish.com (Postfix) with ESMTP id 418581A0076 for ; Mon, 25 Mar 2013 17:39:58 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1155h) Received: from mail82-va3 (localhost.localdomain [127.0.0.1]) by mail82-va3 (MessageSwitch) id 136423319659809_31632; Mon, 25 Mar 2013 17:39:56 +0000 (UTC) Received: from VA3EHSMHS013.bigfish.com (unknown [10.7.14.254]) by mail82-va3.bigfish.com (Postfix) with ESMTP id 0869432027F for ; Mon, 25 Mar 2013 17:39:56 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS013.bigfish.com (10.7.99.23) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 25 Mar 2013 17:39:55 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.2.328.11; Mon, 25 Mar 2013 17:39:54 +0000 Received: from oslab-l1.am.freescale.net ([10.214.80.134]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r2PHdfis011727; Mon, 25 Mar 2013 10:39:53 -0700 From: York Sun To: Date: Mon, 25 Mar 2013 10:39:35 -0700 Message-ID: <1364233180-31149-13-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1364233180-31149-1-git-send-email-yorksun@freescale.com> References: <1364233180-31149-1-git-send-email-yorksun@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: u-boot@lists.denx.de, York Sun Subject: [U-Boot] [Patch v2, batch 3 13/17] powerpc/mpc8xxx: Allow board file to override DDR address assignment X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 1a8d593..7a8636d 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -186,7 +186,7 @@ const char * step_to_string(unsigned int step) { return step_string_tbl[s]; } -unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, +static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, unsigned int dbw_cap_adj[]) { int i, j; @@ -354,6 +354,11 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, return total_mem; } +/* Use weak function to allow board file to override the address assignment */ +__attribute__((weak, alias("__step_assign_addresses"))) +unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]); + unsigned long long fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only)