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[U-Boot,v2,batch,3,04/17] powerpc/mpc85xx b8460 PCIe registers are not at QORIQ_CHASSIS2 location

Message ID 1364233180-31149-4-git-send-email-yorksun@freescale.com
State Superseded
Delegated to: Andy Fleming
Headers show

Commit Message

York Sun March 25, 2013, 5:39 p.m. UTC 
From: Ed Swarthout <ed.swarthout@freescale.com>

Even B4860 has chassis generation 2, but its PCIe registers are at
the same location as other corenet SoCs.

Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
---
 arch/powerpc/include/asm/immap_85xx.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 0cada07..e0e4e1d 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2954,7 +2954,7 @@  struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000