Patchwork [U-Boot,6/6] RFC: am335x: enable falcon boot mode for mmc (raw and fat)

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Submitter Peter Korsgaard
Date March 24, 2013, 9:51 p.m.
Message ID <1364161893-31570-7-git-send-email-peter.korsgaard@barco.com>
Download mbox | patch
Permalink /patch/230497/
State Superseded
Delegated to: Tom Rini
Headers show

Comments

Peter Korsgaard - March 24, 2013, 9:51 p.m.
Jump into full u-boot mode if a 'c' character is received on the uart.

We need to adjust the spl bss/malloc area to not overlap with the
loadaddr of the kernel (sdram + 32k), so move it past u-boot instead.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
---
 board/ti/am335x/board.c      |    9 +++++++++
 include/configs/am335x_evm.h |   25 +++++++++++++++++++++++--
 2 files changed, 32 insertions(+), 2 deletions(-)
Tom Rini - March 27, 2013, 7:43 p.m.
On Sun, Mar 24, 2013 at 10:51:33PM +0100, Peter Korsgaard wrote:

> Jump into full u-boot mode if a 'c' character is received on the uart.
> 
> We need to adjust the spl bss/malloc area to not overlap with the
> loadaddr of the kernel (sdram + 32k), so move it past u-boot instead.
> 
> Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[snip]
> +/* raw mmc */
> +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0xa00 /* address 0xa0000 */
> +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
> +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */

Did you also test raw mode?  Also, why 0xa00?  U-Boot is 0x300 -> 0x500,
and one might say throw a redundant copy at 0x500 -> 0x700.  But we
don't do 4 copy redundancy in U-Boot, just 2 usually.

> +/* dummy defines to keep spl_nand.c happy */
> +#define CONFIG_CMD_SPL_NAND_OFS			0
> +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0
> +#define CONFIG_CMD_SPL_WRITE_SIZE		0

We should do some real defines here while at it, since the GP EVM has
NAND :)
Peter Korsgaard - March 27, 2013, 7:57 p.m.
>>>>> "Tom" == Tom Rini <trini@ti.com> writes:

 Tom> On Sun, Mar 24, 2013 at 10:51:33PM +0100, Peter Korsgaard wrote:
 >> Jump into full u-boot mode if a 'c' character is received on the uart.
 >> 
 >> We need to adjust the spl bss/malloc area to not overlap with the
 >> loadaddr of the kernel (sdram + 32k), so move it past u-boot instead.
 >> 
 >> Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
 Tom> [snip]
 >> +/* raw mmc */
 >> +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0xa00 /* address 0xa0000 */
 >> +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
 >> +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */

 Tom> Did you also test raw mode?

Yes, I did. I'm personally most interested in raw mode because of the 4x
redundant MLO handling.


 Tom> Also, why 0xa00?  U-Boot is 0x300 -> 0x500,
 Tom> and one might say throw a redundant copy at 0x500 -> 0x700.  But we
 Tom> don't do 4 copy redundancy in U-Boot, just 2 usually.

No particular reason, 0x700 should work as well. As mentioned, this was
just a proof of concept to be able to test it.


 >> +/* dummy defines to keep spl_nand.c happy */
 >> +#define CONFIG_CMD_SPL_NAND_OFS			0
 >> +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0
 >> +#define CONFIG_CMD_SPL_WRITE_SIZE		0

 Tom> We should do some real defines here while at it, since the GP EVM has
 Tom> NAND :)

Yes. It's a bit unfortunate that CONFIG_SPL_OS_BOOT is a global setting,
so you need all the various falcon boot related defines even if you
don't plan on using them.

I can try to come up with sensible NAND values, but I don't have a EVM
to test.
Tom Rini - March 27, 2013, 8:19 p.m.
On Wed, Mar 27, 2013 at 08:57:05PM +0100, Peter Korsgaard wrote:
> >>>>> "Tom" == Tom Rini <trini@ti.com> writes:
> 
>  Tom> On Sun, Mar 24, 2013 at 10:51:33PM +0100, Peter Korsgaard wrote:
>  >> Jump into full u-boot mode if a 'c' character is received on the uart.
>  >> 
>  >> We need to adjust the spl bss/malloc area to not overlap with the
>  >> loadaddr of the kernel (sdram + 32k), so move it past u-boot instead.
>  >> 
>  >> Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
>  Tom> [snip]
>  >> +/* raw mmc */
>  >> +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0xa00 /* address 0xa0000 */
>  >> +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
>  >> +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */
> 
>  Tom> Did you also test raw mode?
> 
> Yes, I did. I'm personally most interested in raw mode because of the 4x
> redundant MLO handling.

Note that you only get 3 on RAW mode because we place U-Boot (by
default) in the fourth slot.  I noticed this recently but was hesitant
to break possible deployed setups (in beagle land).  RAW mode isnt' well
documented, but it is in a few places.  For your device I imagine you
could fix things however.

>  Tom> Also, why 0xa00?  U-Boot is 0x300 -> 0x500,
>  Tom> and one might say throw a redundant copy at 0x500 -> 0x700.  But we
>  Tom> don't do 4 copy redundancy in U-Boot, just 2 usually.
> 
> No particular reason, 0x700 should work as well. As mentioned, this was
> just a proof of concept to be able to test it.

Right.  And I'd love to see bootcount or similar updated so that we can
try redundant copies of U-Boot.

>  >> +/* dummy defines to keep spl_nand.c happy */
>  >> +#define CONFIG_CMD_SPL_NAND_OFS			0
>  >> +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0
>  >> +#define CONFIG_CMD_SPL_WRITE_SIZE		0
> 
>  Tom> We should do some real defines here while at it, since the GP EVM has
>  Tom> NAND :)
> 
> Yes. It's a bit unfortunate that CONFIG_SPL_OS_BOOT is a global setting,
> so you need all the various falcon boot related defines even if you
> don't plan on using them.
> 
> I can try to come up with sensible NAND values, but I don't have a EVM
> to test.

Well, CONFIG_SYS_NAND_SPL_KERNEL_OFFS would be where we say nandimgsrc
is in env.  Stefano, looking at twister, the spl export looks like it
goes right at the start of the rootfs, isn't that bad?  Or at least,
luck?
Peter Korsgaard - March 27, 2013, 8:35 p.m.
>>>>> "Tom" == Tom Rini <trini@ti.com> writes:

Hi,

 >> Yes, I did. I'm personally most interested in raw mode because of
 >> the 4x redundant MLO handling.

 Tom> Note that you only get 3 on RAW mode because we place U-Boot (by
 Tom> default) in the fourth slot.  I noticed this recently but was hesitant
 Tom> to break possible deployed setups (in beagle land).  RAW mode isnt' well
 Tom> documented, but it is in a few places.  For your device I imagine you
 Tom> could fix things however.

And you possibly lose the first if you need a DOS style MBR, but that's
OK, I just want to be able to field upgrade the MLO without risks, so 2
is enough.


 >> No particular reason, 0x700 should work as well. As mentioned, this was
 >> just a proof of concept to be able to test it.

 Tom> Right.  And I'd love to see bootcount or similar updated so that
 Tom> we can try redundant copies of U-Boot.

Me too. I'll do some work on it in the relatively near future. I haven't
looked enough into it yet to know if bootcount is enough, or if I would
need custom SPL logic (basically a platform specific spl board_init_r).

The behaviour I would like to have is:

- eMMC split in two parts, and everything (u-boot/linux/rootfs) doubled

- SPL reads a flag somewhere (probably a raw eMMC sector) to decide if
  it should boot low or high uImage / u-boot

- On error (reset because of watchdog, bootcount, ..?) it falls back to
  the other part

- On upgrades the currently unused part is written and the boot flag
  changed.

That's AFAIK currently not possible to do with SPL, as the boot
addresses are build time defines.


 >> I can try to come up with sensible NAND values, but I don't have a EVM
 >> to test.

 Tom> Well, CONFIG_SYS_NAND_SPL_KERNEL_OFFS would be where we say nandimgsrc
 Tom> is in env.  Stefano, looking at twister, the spl export looks like it
 Tom> goes right at the start of the rootfs, isn't that bad?  Or at least,
 Tom> luck?

You mean nandsrcaddr, right? CONFIG_CMD_SPL_NAND_OFS just need to be
somewhere unused on the nand.
Peter Korsgaard - April 10, 2013, 8:49 a.m.
>>>>> "Peter" == Peter Korsgaard <jacmet@sunsite.dk> writes:

Hi,

 Tom> We should do some real defines here while at it, since the GP EVM
 Tom> has NAND :)

 Peter> Yes. It's a bit unfortunate that CONFIG_SPL_OS_BOOT is a global
 Peter> setting, so you need all the various falcon boot related defines
 Peter> even if you don't plan on using them.

 Peter> I can try to come up with sensible NAND values, but I don't have
 Peter> a EVM to test.

Any comments on patch 1-5? Tom, do you want me to send an update to
patch 6 with some more sensible nand parameters?

Patch

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index f4b972b..5efbf3f 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -263,6 +263,15 @@  static struct emif_regs ddr3_evm_emif_reg_data = {
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
 };
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return (serial_tstc() && serial_getc() == 'c');
+}
+#endif
+
 #endif
 
 /*
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 9eada95..26c500a 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -259,13 +259,34 @@ 
 #define CONFIG_SPL_MAX_SIZE		(101 * 1024)
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
 
-#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80a00000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* fat */
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME		"args"
+#define CONFIG_SYS_SPL_ARGS_ADDR		(PHYS_DRAM_1 + 0x100)
+
+/* raw mmc */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0xa00 /* address 0xa0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */
+
+/* dummy defines to keep spl_nand.c happy */
+#define CONFIG_CMD_SPL_NAND_OFS			0
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0
+#define CONFIG_CMD_SPL_WRITE_SIZE		0
+
+#endif
+
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
@@ -327,7 +348,7 @@ 
  * other needs.
  */
 #define CONFIG_SYS_TEXT_BASE		0x80800000
-#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80a08000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 
 /* Since SPL did pll and ddr initialization for us,