From patchwork Fri Mar 22 18:48:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 230242 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 2A5EA2C00CC for ; Sat, 23 Mar 2013 05:48:52 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=default; b=KEaSj4RFjXSi78kmJBnN04gKXX9RSVoHwETe/1IFL96NPa C8hQdObfdru/x1xdpUx8l7R9ciqVEcaYkSFHYDicnECiYjD8pjM8wDCCygSJI8+z TGZNrBeBZGKCY63Wc7R+jk1d2s1IAhu0MZN8IgvcMwUVWyTb9JKgN/kTD61TA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; s= default; bh=WA5ubpNy99EH5AnA4VErOGSINAQ=; b=NF2BUCpbPHq6LM9ZbSJk YLv8sUwslwRhDojRZo79AnqNHZhWDV5lWAPUIPnatMnjYnOWF+3ayY4ut3BAX+cg 21BuDbmAW/Yevv7t2UHey2nJsgF98/8MHI1SMDcW0YgXAD0ZPDgtZq3PHb+8ZB9Q /UsNvRKexDubEGqQXgeEk1k= Received: (qmail 4307 invoked by alias); 22 Mar 2013 18:48:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 4279 invoked by uid 89); 22 Mar 2013 18:48:30 -0000 X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_OV, TW_ZJ autolearn=ham version=3.3.1 Received: from mail-ob0-f177.google.com (HELO mail-ob0-f177.google.com) (209.85.214.177) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Fri, 22 Mar 2013 18:48:26 +0000 Received: by mail-ob0-f177.google.com with SMTP id eh20so4247876obb.22 for ; Fri, 22 Mar 2013 11:48:25 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.1.73 with SMTP id 9mr3007598oek.129.1363978105058; Fri, 22 Mar 2013 11:48:25 -0700 (PDT) Received: by 10.182.49.68 with HTTP; Fri, 22 Mar 2013 11:48:24 -0700 (PDT) Date: Fri, 22 Mar 2013 19:48:24 +0100 Message-ID: Subject: [PATCH 4/n, i386]: Merge and rewrite MMX move patterns using x64 and nox64 isa attribute From: Uros Bizjak To: gcc-patches@gcc.gnu.org X-Virus-Found: No Hello! Attached patch merges _rex64 MMX move patterns with base MMX move patters using x64 and nox64 isa attribute. Additionally, the patch rewrites MMX move patterns to look like DImove move pattern (keeping all decorations of various alternatives), introducing all recent improvements. The patch also handles MMX/SSE interunit moves in a correct way for non-TARGET_INTER_UNIT_MOVES targets (this is the reason for testsuite change). A follow-up patch will merge V2SF move pattern. 2013-03-22 Uros Bizjak * config/i386/sse.md (*mov_internal): Merge with *mov_internal_rex64. Use x64 and nox64 isa attributes. Emit insn template depending on type attribute. Use HAVE_AS_IX86_INTERUNIT_MOVQ to handle broken assemblers that require movd instead of movq mnemonic for interunit moves. Rewrite mode attribute calculation. Remove unit attribute calculation. Set prefix attribute to maybe_vex for sselog1 and ssemov types. Set prefix_data16 attribute for DImode ssemov types. Use Ym instead of y for SSE-MMX conversion alternatives. Reorder operand constraints. testsuite/ChangeLog: 2013-03-22 Uros Bizjak * gcc.target/i386/pr22152.c (dg-options): Add -mtune=core2. Patch was tested on x86_64-pc-linux-gnu {,-m32} and committed to mainline. Uros. Index: config/i386/mmx.md =================================================================== --- config/i386/mmx.md (revision 196970) +++ config/i386/mmx.md (working copy) @@ -76,129 +76,127 @@ DONE; }) -;; movd instead of movq is required to handle broken assemblers. -(define_insn "*mov_internal_rex64" +(define_insn "*mov_internal" [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" - "=rm,r,!?y,!y,!?y,m ,!y ,*x,x,x ,m,r ,Yi") + "=r ,o ,r,r ,m ,!?y,!y,!?y,m ,x,x,x,m,*x,*x,*x,m ,r ,Yi,!Ym,*Yi") (match_operand:MMXMODEI8 1 "vector_move_operand" - "Cr ,m,C ,!y,m ,!?y,*x,!y ,C,xm,x,Yi,r"))] - "TARGET_64BIT && TARGET_MMX + "rCo,rC,C,rm,rC,C ,!y,m ,!?y,C,x,m,x,C ,*x,m ,*x,Yi,r ,*Yi,!Ym"))] + "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "@ - mov{q}\t{%1, %0|%0, %1} - mov{q}\t{%1, %0|%0, %1} - pxor\t%0, %0 - movq\t{%1, %0|%0, %1} - movq\t{%1, %0|%0, %1} - movq\t{%1, %0|%0, %1} - movdq2q\t{%1, %0|%0, %1} - movq2dq\t{%1, %0|%0, %1} - %vpxor\t%0, %d0 - %vmovq\t{%1, %0|%0, %1} - %vmovq\t{%1, %0|%0, %1} - %vmovd\t{%1, %0|%0, %1} - %vmovd\t{%1, %0|%0, %1}" - [(set (attr "type") +{ + switch (get_attr_type (insn)) + { + case TYPE_MULTI: + return "#"; + + case TYPE_IMOV: + if (get_attr_mode (insn) == MODE_SI) + return "mov{l}\t{%1, %k0|%k0, %1}"; + else + return "mov{q}\t{%1, %0|%0, %1}"; + + case TYPE_MMX: + return "pxor\t%0, %0"; + + case TYPE_MMXMOV: +#ifndef HAVE_AS_IX86_INTERUNIT_MOVQ + /* Handle broken assemblers that require movd instead of movq. */ + if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])) + return "movd\t{%1, %0|%0, %1}"; +#endif + return "movq\t{%1, %0|%0, %1}"; + + case TYPE_SSECVT: + if (SSE_REG_P (operands[0])) + return "movq2dq\t{%1, %0|%0, %1}"; + else + return "movdq2q\t{%1, %0|%0, %1}"; + + case TYPE_SSELOG1: + return standard_sse_constant_opcode (insn, operands[1]); + + case TYPE_SSEMOV: + switch (get_attr_mode (insn)) + { + case MODE_DI: +#ifndef HAVE_AS_IX86_INTERUNIT_MOVQ + /* Handle broken assemblers that require movd instead of movq. */ + if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])) + return "%vmovd\t{%1, %0|%0, %1}"; +#endif + return "%vmovq\t{%1, %0|%0, %1}"; + case MODE_TI: + return "%vmovdqa\t{%1, %0|%0, %1}"; + + case MODE_V2SF: + gcc_assert (!TARGET_AVX); + return "movlps\t{%1, %0|%0, %1}"; + case MODE_V4SF: + return "%vmovaps\t{%1, %0|%0, %1}"; + + default: + gcc_unreachable (); + } + + default: + gcc_unreachable (); + } +} + [(set (attr "isa") (cond [(eq_attr "alternative" "0,1") + (const_string "nox64") + (eq_attr "alternative" "2,3,4,9,10,11,12,17,18") + (const_string "x64") + ] + (const_string "*"))) + (set (attr "type") + (cond [(eq_attr "alternative" "0,1") + (const_string "multi") + (eq_attr "alternative" "2,3,4") (const_string "imov") - (eq_attr "alternative" "2") + (eq_attr "alternative" "5") (const_string "mmx") - (eq_attr "alternative" "3,4,5") + (eq_attr "alternative" "6,7,8") (const_string "mmxmov") - (eq_attr "alternative" "6,7") + (eq_attr "alternative" "9,13") + (const_string "sselog1") + (eq_attr "alternative" "19,20") (const_string "ssecvt") - (eq_attr "alternative" "8") - (const_string "sselog1") ] (const_string "ssemov"))) - (set (attr "unit") - (if_then_else (eq_attr "alternative" "6,7") - (const_string "mmx") - (const_string "*"))) - (set (attr "prefix_rep") - (if_then_else (eq_attr "alternative" "6,7,9") + (set (attr "prefix_rex") + (if_then_else (eq_attr "alternative" "17,18") (const_string "1") (const_string "*"))) - (set (attr "prefix_data16") - (if_then_else (eq_attr "alternative" "10,11,12") - (const_string "1") - (const_string "*"))) - (set (attr "prefix_rex") - (if_then_else (eq_attr "alternative" "9,10") - (symbol_ref "x86_extended_reg_mentioned_p (insn)") - (const_string "*"))) (set (attr "prefix") - (if_then_else (eq_attr "alternative" "8,9,10,11,12") + (if_then_else (eq_attr "type" "sselog1,ssemov") (const_string "maybe_vex") (const_string "orig"))) - (set_attr "mode" "DI")]) - -(define_insn "*mov_internal" - [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" - "=!?y,!y,!?y,m ,!y,*x,*x,*x ,m ,*x,*x,*x,m ,r ,m") - (match_operand:MMXMODEI8 1 "vector_move_operand" - "C ,!y,m ,!?y,*x,!y,C ,*xm,*x,C ,*x,m ,*x,irm,r"))] - "!TARGET_64BIT && TARGET_MMX - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "@ - pxor\t%0, %0 - movq\t{%1, %0|%0, %1} - movq\t{%1, %0|%0, %1} - movq\t{%1, %0|%0, %1} - movdq2q\t{%1, %0|%0, %1} - movq2dq\t{%1, %0|%0, %1} - %vpxor\t%0, %d0 - %vmovq\t{%1, %0|%0, %1} - %vmovq\t{%1, %0|%0, %1} - xorps\t%0, %0 - movaps\t{%1, %0|%0, %1} - movlps\t{%1, %0|%0, %1} - movlps\t{%1, %0|%0, %1} - # - #" - [(set (attr "isa") - (cond [(eq_attr "alternative" "4,5,6,7,8") - (const_string "sse2") - (eq_attr "alternative" "9,10,11,12") - (const_string "noavx") - ] - (const_string "*"))) - (set (attr "type") - (cond [(eq_attr "alternative" "0") - (const_string "mmx") - (eq_attr "alternative" "1,2,3") - (const_string "mmxmov") - (eq_attr "alternative" "4,5") - (const_string "ssecvt") - (eq_attr "alternative" "6,9") - (const_string "sselog1") - (eq_attr "alternative" "13,14") - (const_string "multi") - ] - (const_string "ssemov"))) - (set (attr "unit") - (if_then_else (eq_attr "alternative" "4,5") - (const_string "mmx") - (const_string "*"))) - (set (attr "prefix_rep") - (if_then_else - (ior (eq_attr "alternative" "4,5") - (and (eq_attr "alternative" "7") - (not (match_test "TARGET_AVX")))) - (const_string "1") - (const_string "*"))) (set (attr "prefix_data16") (if_then_else - (and (eq_attr "alternative" "8") - (not (match_test "TARGET_AVX"))) + (and (eq_attr "type" "ssemov") (eq_attr "mode" "DI")) (const_string "1") (const_string "*"))) - (set (attr "prefix") - (if_then_else (eq_attr "alternative" "6,7,8") - (const_string "maybe_vex") - (const_string "orig"))) - (set_attr "mode" "DI,DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")]) + (set (attr "mode") + (cond [(eq_attr "alternative" "2") + (const_string "SI") + (eq_attr "alternative" "9,10,13,14") + (cond [(ior (not (match_test "TARGET_SSE2")) + (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) + (const_string "V4SF") + (match_test "TARGET_AVX") + (const_string "TI") + (match_test "optimize_function_for_size_p (cfun)") + (const_string "V4SF") + ] + (const_string "TI")) + (and (eq_attr "alternative" "11,12,15,16") + (not (match_test "TARGET_SSE2"))) + (const_string "V2SF") + ] + (const_string "DI")))]) + (define_expand "movv2sf" [(set (match_operand:V2SF 0 "nonimmediate_operand") (match_operand:V2SF 1 "nonimmediate_operand"))] Index: testsuite/gcc.target/i386/pr22152.c =================================================================== --- testsuite/gcc.target/i386/pr22152.c (revision 196970) +++ testsuite/gcc.target/i386/pr22152.c (working copy) @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -msse2" } */ -/* { dg-options "-O2 -msse2 -mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */ +/* { dg-options "-O2 -msse2 -mtune=core2" } */ +/* { dg-additional-options "-mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */ /* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */ #include