Patchwork [U-Boot,1/3,V4] EXYNOS5: Add gpio pin numbering feature

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Submitter Rajeshwari Birje
Date March 21, 2013, 11:33 a.m.
Message ID <1363865621-7570-2-git-send-email-rajeshwari.s@samsung.com>
Download mbox | patch
Permalink /patch/229628/
State Changes Requested
Delegated to: Minkyu Kang
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Comments

Rajeshwari Birje - March 21, 2013, 11:33 a.m.
This patch adds support for gpio pin numbering support on
EXYNOS5250
To have consistent 0..n-1 GPIO numbering the banks are divided
into different parts where ever they have holes in them.

Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
Changes in V2:
        - none.
Changes in V3:
        - none.
Changes in V4:
	- To have consistent 0..n-1 GPIO numbering the banks are divided
	into different parts where ever they have holes in them.
	- Combined previous patch 1 and 2 into single patch.
 arch/arm/cpu/armv7/exynos/pinmux.c      |  148 +++++-------
 arch/arm/include/asm/arch-exynos/cpu.h  |   10 +-
 arch/arm/include/asm/arch-exynos/gpio.h |  376 ++++++++++++++++++++++++++++++-
 board/samsung/smdk5250/smdk5250.c       |   24 +--
 drivers/gpio/s5p_gpio.c                 |   65 ++++++-
 5 files changed, 508 insertions(+), 115 deletions(-)
Minkyu Kang - April 1, 2013, 11:57 a.m.
On 21/03/13 20:33, Rajeshwari Shinde wrote:
> This patch adds support for gpio pin numbering support on
> EXYNOS5250
> To have consistent 0..n-1 GPIO numbering the banks are divided
> into different parts where ever they have holes in them.
> 
> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> Changes in V2:
>         - none.
> Changes in V3:
>         - none.
> Changes in V4:
> 	- To have consistent 0..n-1 GPIO numbering the banks are divided
> 	into different parts where ever they have holes in them.
> 	- Combined previous patch 1 and 2 into single patch.
>  arch/arm/cpu/armv7/exynos/pinmux.c      |  148 +++++-------
>  arch/arm/include/asm/arch-exynos/cpu.h  |   10 +-
>  arch/arm/include/asm/arch-exynos/gpio.h |  376 ++++++++++++++++++++++++++++++-
>  board/samsung/smdk5250/smdk5250.c       |   24 +--
>  drivers/gpio/s5p_gpio.c                 |   65 ++++++-
>  5 files changed, 508 insertions(+), 115 deletions(-)
> 
> diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
> index 656bf4a..1b882cb 100644
> --- a/drivers/gpio/s5p_gpio.c
> +++ b/drivers/gpio/s5p_gpio.c
> @@ -36,6 +36,27 @@
>  #define RATE_MASK(x)		(0x1 << (x + 16))
>  #define RATE_SET(x)		(0x1 << (x + 16))
>  
> +
> +struct gpio_info {
> +	unsigned int reg_addr;	/* Address of register for this part */
> +	unsigned int max_gpio;	/* Maximum GPIO in this part */
> +};
> +
> +#ifdef CONFIG_EXYNOS5

I think, this ifdef is unnecessary.

> +static const struct gpio_info gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {

maybe it should be exynos5_gpio_data?

> +	{ EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
> +	{ EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
> +	{ EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
> +	{ EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
> +	{ EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
> +	{ EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
> +	{ EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
> +	{ EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
> +};
> +
> +#define HAVE_GENERIC_GPIO
> +#endif
> +
>  void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
>  {
>  	unsigned int value;
> @@ -141,7 +162,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
>  
>  	writel(value, &bank->drv);
>  }
> -
> +#ifdef HAVE_GENERIC_GPIO
> +static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)

please consider exynos4 also.

> +{
> +	const struct gpio_info *data;
> +	unsigned int upto;
> +	int i;
> +
> +	for (i = upto = 0, data = gpio_data; i < EXYNOS5_GPIO_NUM_PARTS;
> +			i++, upto = data->max_gpio, data++) {
> +		debug("i=%d, upto=%d\n", i, upto);
> +		if (gpio < data->max_gpio) {
> +			struct s5p_gpio_bank *bank;
> +			bank = (struct s5p_gpio_bank *)data->reg_addr;
> +			bank += (gpio - upto) / GPIO_PER_BANK;
> +			debug("   gpio=%d, bank=%p\n", gpio, bank);
> +			return bank;
> +		}
> +	}
> +#ifndef CONFIG_SPL_BUILD
> +	assert(gpio < EXYNOS5_GPIO_MAX_PORT);	/* ...which it will not be */
> +#endif
> +	return NULL;
> +}
> +#else
>  struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
>  {
>  	int bank;
> @@ -151,6 +195,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
>  	bank *= sizeof(struct s5p_gpio_bank);
>  	return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
>  }
> +#endif
>  
>  int s5p_gpio_get_pin(unsigned gpio)
>  {
> @@ -196,3 +241,21 @@ int gpio_set_value(unsigned gpio, int value)
>  
>  	return 0;
>  }
> +
> +void gpio_set_pull(int gpio, int mode)
> +{
> +	s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
> +			s5p_gpio_get_pin(gpio), mode);
> +}
> +
> +void gpio_set_drv(int gpio, int mode)
> +{
> +	s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
> +			s5p_gpio_get_pin(gpio), mode);
> +}
> +
> +void gpio_cfg_pin(int gpio, int cfg)
> +{
> +	s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
> +			s5p_gpio_get_pin(gpio), cfg);
> +}
> 

Thanks,
Minkyu Kang.
Rajeshwari Birje - April 2, 2013, 5:08 a.m.
Hi Minkyu Kang,

Thank you for comments.

On Mon, Apr 1, 2013 at 5:27 PM, Minkyu Kang <mk7.kang@samsung.com> wrote:
> On 21/03/13 20:33, Rajeshwari Shinde wrote:
>> This patch adds support for gpio pin numbering support on
>> EXYNOS5250
>> To have consistent 0..n-1 GPIO numbering the banks are divided
>> into different parts where ever they have holes in them.
>>
>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> ---
>> Changes in V2:
>>         - none.
>> Changes in V3:
>>         - none.
>> Changes in V4:
>>       - To have consistent 0..n-1 GPIO numbering the banks are divided
>>       into different parts where ever they have holes in them.
>>       - Combined previous patch 1 and 2 into single patch.
>>  arch/arm/cpu/armv7/exynos/pinmux.c      |  148 +++++-------
>>  arch/arm/include/asm/arch-exynos/cpu.h  |   10 +-
>>  arch/arm/include/asm/arch-exynos/gpio.h |  376 ++++++++++++++++++++++++++++++-
>>  board/samsung/smdk5250/smdk5250.c       |   24 +--
>>  drivers/gpio/s5p_gpio.c                 |   65 ++++++-
>>  5 files changed, 508 insertions(+), 115 deletions(-)
>>
>> diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
>> index 656bf4a..1b882cb 100644
>> --- a/drivers/gpio/s5p_gpio.c
>> +++ b/drivers/gpio/s5p_gpio.c
>> @@ -36,6 +36,27 @@
>>  #define RATE_MASK(x)         (0x1 << (x + 16))
>>  #define RATE_SET(x)          (0x1 << (x + 16))
>>
>> +
>> +struct gpio_info {
>> +     unsigned int reg_addr;  /* Address of register for this part */
>> +     unsigned int max_gpio;  /* Maximum GPIO in this part */
>> +};
>> +
>> +#ifdef CONFIG_EXYNOS5
>
> I think, this ifdef is unnecessary.
I had put this #ifdef as EXYNOS4 will also have a gpio_data structure.
>
>> +static const struct gpio_info gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {
>
> maybe it should be exynos5_gpio_data?
No kept it as gpio_data as it would b easy to call the same from
s5p_gpio_get_bank function and exynos4 will also have a separate
structure.
>
>> +     { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
>> +     { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
>> +     { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
>> +     { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
>> +     { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
>> +     { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
>> +     { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
>> +     { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
>> +};
>> +
>> +#define HAVE_GENERIC_GPIO
>> +#endif
>> +
>>  void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
>>  {
>>       unsigned int value;
>> @@ -141,7 +162,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
>>
>>       writel(value, &bank->drv);
>>  }
>> -
>> +#ifdef HAVE_GENERIC_GPIO
>> +static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
>
> please consider exynos4 also.
Yes will update the same for exynos4 and send as soon as possible.
>
>> +{
>> +     const struct gpio_info *data;
>> +     unsigned int upto;
>> +     int i;
>> +
>> +     for (i = upto = 0, data = gpio_data; i < EXYNOS5_GPIO_NUM_PARTS;
>> +                     i++, upto = data->max_gpio, data++) {
>> +             debug("i=%d, upto=%d\n", i, upto);
>> +             if (gpio < data->max_gpio) {
>> +                     struct s5p_gpio_bank *bank;
>> +                     bank = (struct s5p_gpio_bank *)data->reg_addr;
>> +                     bank += (gpio - upto) / GPIO_PER_BANK;
>> +                     debug("   gpio=%d, bank=%p\n", gpio, bank);
>> +                     return bank;
>> +             }
>> +     }
>> +#ifndef CONFIG_SPL_BUILD
>> +     assert(gpio < EXYNOS5_GPIO_MAX_PORT);   /* ...which it will not be */
>> +#endif
>> +     return NULL;
>> +}
>> +#else
>>  struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
>>  {
>>       int bank;
>> @@ -151,6 +195,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
>>       bank *= sizeof(struct s5p_gpio_bank);
>>       return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
>>  }
>> +#endif
>>
>>  int s5p_gpio_get_pin(unsigned gpio)
>>  {
>> @@ -196,3 +241,21 @@ int gpio_set_value(unsigned gpio, int value)
>>
>>       return 0;
>>  }
>> +
>> +void gpio_set_pull(int gpio, int mode)
>> +{
>> +     s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
>> +                     s5p_gpio_get_pin(gpio), mode);
>> +}
>> +
>> +void gpio_set_drv(int gpio, int mode)
>> +{
>> +     s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
>> +                     s5p_gpio_get_pin(gpio), mode);
>> +}
>> +
>> +void gpio_cfg_pin(int gpio, int cfg)
>> +{
>> +     s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
>> +                     s5p_gpio_get_pin(gpio), cfg);
>> +}
>>
>
> Thanks,
> Minkyu Kang.
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Minkyu Kang - April 2, 2013, 5:19 a.m.
Dear Rajeshwari Birje,

On 02/04/13 14:08, Rajeshwari Birje wrote:
> Hi Minkyu Kang,
> 
> Thank you for comments.
> 
> On Mon, Apr 1, 2013 at 5:27 PM, Minkyu Kang <mk7.kang@samsung.com> wrote:
>> On 21/03/13 20:33, Rajeshwari Shinde wrote:
>>> This patch adds support for gpio pin numbering support on
>>> EXYNOS5250
>>> To have consistent 0..n-1 GPIO numbering the banks are divided
>>> into different parts where ever they have holes in them.
>>>
>>> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
>>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>>> ---
>>> Changes in V2:
>>>         - none.
>>> Changes in V3:
>>>         - none.
>>> Changes in V4:
>>>       - To have consistent 0..n-1 GPIO numbering the banks are divided
>>>       into different parts where ever they have holes in them.
>>>       - Combined previous patch 1 and 2 into single patch.
>>>  arch/arm/cpu/armv7/exynos/pinmux.c      |  148 +++++-------
>>>  arch/arm/include/asm/arch-exynos/cpu.h  |   10 +-
>>>  arch/arm/include/asm/arch-exynos/gpio.h |  376 ++++++++++++++++++++++++++++++-
>>>  board/samsung/smdk5250/smdk5250.c       |   24 +--
>>>  drivers/gpio/s5p_gpio.c                 |   65 ++++++-
>>>  5 files changed, 508 insertions(+), 115 deletions(-)
>>>
>>> diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
>>> index 656bf4a..1b882cb 100644
>>> --- a/drivers/gpio/s5p_gpio.c
>>> +++ b/drivers/gpio/s5p_gpio.c
>>> @@ -36,6 +36,27 @@
>>>  #define RATE_MASK(x)         (0x1 << (x + 16))
>>>  #define RATE_SET(x)          (0x1 << (x + 16))
>>>
>>> +
>>> +struct gpio_info {
>>> +     unsigned int reg_addr;  /* Address of register for this part */
>>> +     unsigned int max_gpio;  /* Maximum GPIO in this part */
>>> +};
>>> +
>>> +#ifdef CONFIG_EXYNOS5
>>
>> I think, this ifdef is unnecessary.
> I had put this #ifdef as EXYNOS4 will also have a gpio_data structure.

Exynos doesn't allow ifdefs on own drivers.
Please don't use it.

>>
>>> +static const struct gpio_info gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {
>>
>> maybe it should be exynos5_gpio_data?
> No kept it as gpio_data as it would b easy to call the same from
> s5p_gpio_get_bank function and exynos4 will also have a separate
> structure.

I suggest that make two structure exynos5_gpio_data and exynos4_gpio_data,
and please remove ifdef.

>>
>>> +     { EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
>>> +     { EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
>>> +     { EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
>>> +     { EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
>>> +     { EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
>>> +     { EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
>>> +     { EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
>>> +     { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
>>> +};
>>> +
>>> +#define HAVE_GENERIC_GPIO
>>> +#endif
>>> +
>>>  void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
>>>  {
>>>       unsigned int value;
>>> @@ -141,7 +162,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
>>>
>>>       writel(value, &bank->drv);
>>>  }
>>> -
>>> +#ifdef HAVE_GENERIC_GPIO
>>> +static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
>>
>> please consider exynos4 also.
> Yes will update the same for exynos4 and send as soon as possible.

So, please modify this function and resend.

>>
>>> +{
>>> +     const struct gpio_info *data;
>>> +     unsigned int upto;
>>> +     int i;
>>> +
>>> +     for (i = upto = 0, data = gpio_data; i < EXYNOS5_GPIO_NUM_PARTS;

here. EXYNOS5 stuff.

>>> +                     i++, upto = data->max_gpio, data++) {
>>> +             debug("i=%d, upto=%d\n", i, upto);
>>> +             if (gpio < data->max_gpio) {
>>> +                     struct s5p_gpio_bank *bank;
>>> +                     bank = (struct s5p_gpio_bank *)data->reg_addr;
>>> +                     bank += (gpio - upto) / GPIO_PER_BANK;
>>> +                     debug("   gpio=%d, bank=%p\n", gpio, bank);
>>> +                     return bank;
>>> +             }
>>> +     }
>>> +#ifndef CONFIG_SPL_BUILD
>>> +     assert(gpio < EXYNOS5_GPIO_MAX_PORT);   /* ...which it will not be */
>>> +#endif
>>> +     return NULL;
>>> +}
>>> +#else
>>>  struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
>>>  {
>>>       int bank;
>>> @@ -151,6 +195,7 @@ struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
>>>       bank *= sizeof(struct s5p_gpio_bank);
>>>       return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
>>>  }
>>> +#endif
>>>
>>>  int s5p_gpio_get_pin(unsigned gpio)
>>>  {
>>> @@ -196,3 +241,21 @@ int gpio_set_value(unsigned gpio, int value)
>>>
>>>       return 0;
>>>  }
>>> +
>>> +void gpio_set_pull(int gpio, int mode)
>>> +{
>>> +     s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
>>> +                     s5p_gpio_get_pin(gpio), mode);
>>> +}
>>> +
>>> +void gpio_set_drv(int gpio, int mode)
>>> +{
>>> +     s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
>>> +                     s5p_gpio_get_pin(gpio), mode);
>>> +}
>>> +
>>> +void gpio_cfg_pin(int gpio, int cfg)
>>> +{
>>> +     s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
>>> +                     s5p_gpio_get_pin(gpio), cfg);
>>> +}
>>>
>>
>> Thanks,
>> Minkyu Kang.
>> _______________________________________________
>> U-Boot mailing list
>> U-Boot@lists.denx.de
>> http://lists.denx.de/mailman/listinfo/u-boot
> 

Thanks,
Minkyu Kang.

Patch

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index bd499b4..02a4d88 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -29,89 +29,77 @@ 
 
 static void exynos5_uart_config(int peripheral)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank;
 	int i, start, count;
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		bank = &gpio1->a0;
-		start = 0;
+		start = EXYNOS5_GPIO_A00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART1:
-		bank = &gpio1->d0;
-		start = 0;
+		start = EXYNOS5_GPIO_D00;
 		count = 4;
 		break;
 	case PERIPH_ID_UART2:
-		bank = &gpio1->a1;
-		start = 0;
+		start = EXYNOS5_GPIO_A10;
 		count = 4;
 		break;
 	case PERIPH_ID_UART3:
-		bank = &gpio1->a1;
-		start = 4;
+		start = EXYNOS5_GPIO_A14;
 		count = 2;
 		break;
 	}
 	for (i = start; i < start + count; i++) {
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+		gpio_set_pull(i, GPIO_PULL_NONE);
+		gpio_cfg_pin(i, GPIO_FUNC(0x2));
 	}
 }
 
 static int exynos5_mmc_config(int peripheral, int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct s5p_gpio_bank *bank, *bank_ext;
-	int i, start = 0, gpio_func = 0;
+	int i, start, start_ext, gpio_func = 0;
 
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		bank = &gpio1->c0;
-		bank_ext = &gpio1->c1;
-		start = 0;
+		start = EXYNOS5_GPIO_C00;
+		start_ext = EXYNOS5_GPIO_C10;
 		gpio_func = GPIO_FUNC(0x2);
 		break;
 	case PERIPH_ID_SDMMC1:
-		bank = &gpio1->c2;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C20;
+		start_ext = 0;
 		break;
 	case PERIPH_ID_SDMMC2:
-		bank = &gpio1->c3;
-		bank_ext = &gpio1->c4;
-		start = 3;
+		start = EXYNOS5_GPIO_C30;
+		start_ext = EXYNOS5_GPIO_C43;
 		gpio_func = GPIO_FUNC(0x3);
 		break;
 	case PERIPH_ID_SDMMC3:
-		bank = &gpio1->c4;
-		bank_ext = NULL;
+		start = EXYNOS5_GPIO_C40;
+		start_ext = 0;
 		break;
 	}
-	if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+	if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) {
 		debug("SDMMC device %d does not support 8bit mode",
 				peripheral);
 		return -1;
 	}
 	if (flags & PINMUX_FLAG_8BIT_MODE) {
-		for (i = start; i <= (start + 3); i++) {
-			s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
-			s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
-			s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+		for (i = start_ext; i <= (start_ext + 3); i++) {
+			gpio_cfg_pin(i, gpio_func);
+			gpio_set_pull(i, GPIO_PULL_UP);
+			gpio_set_drv(i, GPIO_DRV_4X);
 		}
 	}
 	for (i = 0; i < 2; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, GPIO_PULL_NONE);
+		gpio_set_drv(start + i, GPIO_DRV_4X);
 	}
 	for (i = 3; i <= 6; i++) {
-		s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
-		s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
-		s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+		gpio_cfg_pin(start + i, GPIO_FUNC(0x2));
+		gpio_set_pull(start + i, GPIO_PULL_UP);
+		gpio_set_drv(start + i, GPIO_DRV_4X);
 	}
 
 	return 0;
@@ -119,8 +107,6 @@  static int exynos5_mmc_config(int peripheral, int flags)
 
 static void exynos5_sromc_config(int flags)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 	int i;
 
 	/*
@@ -138,13 +124,13 @@  static void exynos5_sromc_config(int flags)
 	 * GPY1[2]	SROM_WAIT(2)
 	 * GPY1[3]	EBI_DATA_RDn(2)
 	 */
-	s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
+	gpio_cfg_pin(EXYNOS5_GPIO_Y00 + (flags & PINMUX_FLAG_BANK),
 				GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
-	s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y04, GPIO_FUNC(2));
+	gpio_cfg_pin(EXYNOS5_GPIO_Y05, GPIO_FUNC(2));
 
 	for (i = 0; i < 4; i++)
-		s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+		gpio_cfg_pin(EXYNOS5_GPIO_Y10 + i, GPIO_FUNC(2));
 
 	/*
 	 * EBI: 8 Addrss Lines
@@ -179,55 +165,52 @@  static void exynos5_sromc_config(int flags)
 	 * GPY6[7]	EBI_DATA[15](2)
 	 */
 	for (i = 0; i < 8; i++) {
-		s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y30 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y30 + i, GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y50 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y50 + i, GPIO_PULL_UP);
 
-		s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
-		s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+		gpio_cfg_pin(EXYNOS5_GPIO_Y60 + i, GPIO_FUNC(2));
+		gpio_set_pull(EXYNOS5_GPIO_Y60 + i, GPIO_PULL_UP);
 	}
 }
 
 static void exynos5_i2c_config(int peripheral, int flags)
 {
 
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-
 	switch (peripheral) {
 	case PERIPH_ID_I2C0:
-		s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B30, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B31, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C1:
-		s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
-		s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B32, GPIO_FUNC(0x2));
+		gpio_cfg_pin(EXYNOS5_GPIO_B33, GPIO_FUNC(0x2));
 		break;
 	case PERIPH_ID_I2C2:
-		s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A06, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A07, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C3:
-		s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A12, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A13, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C4:
-		s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A20, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A21, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C5:
-		s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_A23, GPIO_FUNC(0x3));
 		break;
 	case PERIPH_ID_I2C6:
-		s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
-		s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B13, GPIO_FUNC(0x4));
+		gpio_cfg_pin(EXYNOS5_GPIO_B14, GPIO_FUNC(0x4));
 		break;
 	case PERIPH_ID_I2C7:
-		s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
-		s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B22, GPIO_FUNC(0x3));
+		gpio_cfg_pin(EXYNOS5_GPIO_B23, GPIO_FUNC(0x3));
 		break;
 	}
 }
@@ -235,53 +218,42 @@  static void exynos5_i2c_config(int peripheral, int flags)
 static void exynos5_i2s_config(int peripheral)
 {
 	int i;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 
 	for (i = 0; i < 5; i++)
-		s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+		gpio_cfg_pin(EXYNOS5_GPIO_B00+i, GPIO_FUNC(0x02));
 }
 
 void exynos5_spi_config(int peripheral)
 {
 	int cfg = 0, pin = 0, i;
-	struct s5p_gpio_bank *bank = NULL;
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
-	struct exynos5_gpio_part2 *gpio2 =
-		(struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
 
 	switch (peripheral) {
 	case PERIPH_ID_SPI0:
-		bank = &gpio1->a2;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5_GPIO_A20;
 		break;
 	case PERIPH_ID_SPI1:
-		bank = &gpio1->a2;
 		cfg = GPIO_FUNC(0x2);
-		pin = 4;
+		pin = EXYNOS5_GPIO_A24;
 		break;
 	case PERIPH_ID_SPI2:
-		bank = &gpio1->b1;
 		cfg = GPIO_FUNC(0x5);
-		pin = 1;
+		pin = EXYNOS5_GPIO_B11;
 		break;
 	case PERIPH_ID_SPI3:
-		bank = &gpio2->f1;
 		cfg = GPIO_FUNC(0x2);
-		pin = 0;
+		pin = EXYNOS5_GPIO_F10;
 		break;
 	case PERIPH_ID_SPI4:
 		for (i = 0; i < 2; i++) {
-			s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
-			s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_F02 + i, GPIO_FUNC(0x4));
+			gpio_cfg_pin(EXYNOS5_GPIO_E04 + i, GPIO_FUNC(0x4));
 		}
 		break;
 	}
 	if (peripheral != PERIPH_ID_SPI4) {
 		for (i = pin; i < pin + 4; i++)
-			s5p_gpio_cfg_pin(bank, i, cfg);
+			gpio_cfg_pin(i, cfg);
 	}
 }
 
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index eb34422..5f08f11 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -99,7 +99,7 @@ 
 /* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING		0x10000
 
-#define EXYNOS5_GPIO_PART4_BASE		0x03860000
+#define EXYNOS5_GPIO_PART8_BASE		0x03860000
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
 #define EXYNOS5_POWER_BASE		0x10040000
@@ -108,9 +108,13 @@ 
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_DMC_PHY0_BASE		0x10C00000
 #define EXYNOS5_DMC_PHY1_BASE		0x10C10000
-#define EXYNOS5_GPIO_PART3_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE		0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE		0x10D100C0
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_GPIO_PART2_BASE		0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE		0x11400C00
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
 #define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
 #define EXYNOS5_USBPHY_BASE		0x12130000
@@ -123,7 +127,7 @@ 
 #define EXYNOS5_I2S_BASE		0x12D60000
 #define EXYNOS5_PWMTIMER_BASE		0x12DD0000
 #define EXYNOS5_SPI_ISP_BASE		0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE		0x13400000
+#define EXYNOS5_GPIO_PART4_BASE		0x13400000
 #define EXYNOS5_FIMD_BASE		0x14400000
 #define EXYNOS5_DP_BASE			0x145B0000
 
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index cfe1024..e1e59f1 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -161,16 +161,20 @@  struct exynos5_gpio_part1 {
 	struct s5p_gpio_bank y4;
 	struct s5p_gpio_bank y5;
 	struct s5p_gpio_bank y6;
-	struct s5p_gpio_bank res1[0x3];
+};
+
+struct exynos5_gpio_part2 {
 	struct s5p_gpio_bank c4;
-	struct s5p_gpio_bank res2[0x48];
+};
+
+struct exynos5_gpio_part3 {
 	struct s5p_gpio_bank x0;
 	struct s5p_gpio_bank x1;
 	struct s5p_gpio_bank x2;
 	struct s5p_gpio_bank x3;
 };
 
-struct exynos5_gpio_part2 {
+struct exynos5_gpio_part4 {
 	struct s5p_gpio_bank e0;
 	struct s5p_gpio_bank e1;
 	struct s5p_gpio_bank f0;
@@ -182,20 +186,26 @@  struct exynos5_gpio_part2 {
 	struct s5p_gpio_bank h1;
 };
 
-struct exynos5_gpio_part3 {
+struct exynos5_gpio_part5 {
 	struct s5p_gpio_bank v0;
 	struct s5p_gpio_bank v1;
-	struct s5p_gpio_bank res1[0x1];
+};
+
+struct exynos5_gpio_part6 {
 	struct s5p_gpio_bank v2;
 	struct s5p_gpio_bank v3;
-	struct s5p_gpio_bank res2[0x1];
+};
+
+struct exynos5_gpio_part7 {
 	struct s5p_gpio_bank v4;
 };
 
-struct exynos5_gpio_part4 {
+struct exynos5_gpio_part8 {
 	struct s5p_gpio_bank z;
 };
 
+#define EXYNOS5_GPIO_NUM_PARTS	8
+
 /* functions */
 void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
 void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
@@ -272,6 +282,352 @@  void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 	    - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
 	  * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
 
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum exynos5_gpio_pin {
+	/* GPIO_PART1_STARTS */
+	EXYNOS5_GPIO_A00,
+	EXYNOS5_GPIO_A01,
+	EXYNOS5_GPIO_A02,
+	EXYNOS5_GPIO_A03,
+	EXYNOS5_GPIO_A04,
+	EXYNOS5_GPIO_A05,
+	EXYNOS5_GPIO_A06,
+	EXYNOS5_GPIO_A07,
+	EXYNOS5_GPIO_A10,
+	EXYNOS5_GPIO_A11,
+	EXYNOS5_GPIO_A12,
+	EXYNOS5_GPIO_A13,
+	EXYNOS5_GPIO_A14,
+	EXYNOS5_GPIO_A15,
+	EXYNOS5_GPIO_A16,
+	EXYNOS5_GPIO_A17,
+	EXYNOS5_GPIO_A20,
+	EXYNOS5_GPIO_A21,
+	EXYNOS5_GPIO_A22,
+	EXYNOS5_GPIO_A23,
+	EXYNOS5_GPIO_A24,
+	EXYNOS5_GPIO_A25,
+	EXYNOS5_GPIO_A26,
+	EXYNOS5_GPIO_A27,
+	EXYNOS5_GPIO_B00,
+	EXYNOS5_GPIO_B01,
+	EXYNOS5_GPIO_B02,
+	EXYNOS5_GPIO_B03,
+	EXYNOS5_GPIO_B04,
+	EXYNOS5_GPIO_B05,
+	EXYNOS5_GPIO_B06,
+	EXYNOS5_GPIO_B07,
+	EXYNOS5_GPIO_B10,
+	EXYNOS5_GPIO_B11,
+	EXYNOS5_GPIO_B12,
+	EXYNOS5_GPIO_B13,
+	EXYNOS5_GPIO_B14,
+	EXYNOS5_GPIO_B15,
+	EXYNOS5_GPIO_B16,
+	EXYNOS5_GPIO_B17,
+	EXYNOS5_GPIO_B20,
+	EXYNOS5_GPIO_B21,
+	EXYNOS5_GPIO_B22,
+	EXYNOS5_GPIO_B23,
+	EXYNOS5_GPIO_B24,
+	EXYNOS5_GPIO_B25,
+	EXYNOS5_GPIO_B26,
+	EXYNOS5_GPIO_B27,
+	EXYNOS5_GPIO_B30,
+	EXYNOS5_GPIO_B31,
+	EXYNOS5_GPIO_B32,
+	EXYNOS5_GPIO_B33,
+	EXYNOS5_GPIO_B34,
+	EXYNOS5_GPIO_B35,
+	EXYNOS5_GPIO_B36,
+	EXYNOS5_GPIO_B37,
+	EXYNOS5_GPIO_C00,
+	EXYNOS5_GPIO_C01,
+	EXYNOS5_GPIO_C02,
+	EXYNOS5_GPIO_C03,
+	EXYNOS5_GPIO_C04,
+	EXYNOS5_GPIO_C05,
+	EXYNOS5_GPIO_C06,
+	EXYNOS5_GPIO_C07,
+	EXYNOS5_GPIO_C10,
+	EXYNOS5_GPIO_C11,
+	EXYNOS5_GPIO_C12,
+	EXYNOS5_GPIO_C13,
+	EXYNOS5_GPIO_C14,
+	EXYNOS5_GPIO_C15,
+	EXYNOS5_GPIO_C16,
+	EXYNOS5_GPIO_C17,
+	EXYNOS5_GPIO_C20,
+	EXYNOS5_GPIO_C21,
+	EXYNOS5_GPIO_C22,
+	EXYNOS5_GPIO_C23,
+	EXYNOS5_GPIO_C24,
+	EXYNOS5_GPIO_C25,
+	EXYNOS5_GPIO_C26,
+	EXYNOS5_GPIO_C27,
+	EXYNOS5_GPIO_C30,
+	EXYNOS5_GPIO_C31,
+	EXYNOS5_GPIO_C32,
+	EXYNOS5_GPIO_C33,
+	EXYNOS5_GPIO_C34,
+	EXYNOS5_GPIO_C35,
+	EXYNOS5_GPIO_C36,
+	EXYNOS5_GPIO_C37,
+	EXYNOS5_GPIO_D00,
+	EXYNOS5_GPIO_D01,
+	EXYNOS5_GPIO_D02,
+	EXYNOS5_GPIO_D03,
+	EXYNOS5_GPIO_D04,
+	EXYNOS5_GPIO_D05,
+	EXYNOS5_GPIO_D06,
+	EXYNOS5_GPIO_D07,
+	EXYNOS5_GPIO_D10,
+	EXYNOS5_GPIO_D11,
+	EXYNOS5_GPIO_D12,
+	EXYNOS5_GPIO_D13,
+	EXYNOS5_GPIO_D14,
+	EXYNOS5_GPIO_D15,
+	EXYNOS5_GPIO_D16,
+	EXYNOS5_GPIO_D17,
+	EXYNOS5_GPIO_Y00,
+	EXYNOS5_GPIO_Y01,
+	EXYNOS5_GPIO_Y02,
+	EXYNOS5_GPIO_Y03,
+	EXYNOS5_GPIO_Y04,
+	EXYNOS5_GPIO_Y05,
+	EXYNOS5_GPIO_Y06,
+	EXYNOS5_GPIO_Y07,
+	EXYNOS5_GPIO_Y10,
+	EXYNOS5_GPIO_Y11,
+	EXYNOS5_GPIO_Y12,
+	EXYNOS5_GPIO_Y13,
+	EXYNOS5_GPIO_Y14,
+	EXYNOS5_GPIO_Y15,
+	EXYNOS5_GPIO_Y16,
+	EXYNOS5_GPIO_Y17,
+	EXYNOS5_GPIO_Y20,
+	EXYNOS5_GPIO_Y21,
+	EXYNOS5_GPIO_Y22,
+	EXYNOS5_GPIO_Y23,
+	EXYNOS5_GPIO_Y24,
+	EXYNOS5_GPIO_Y25,
+	EXYNOS5_GPIO_Y26,
+	EXYNOS5_GPIO_Y27,
+	EXYNOS5_GPIO_Y30,
+	EXYNOS5_GPIO_Y31,
+	EXYNOS5_GPIO_Y32,
+	EXYNOS5_GPIO_Y33,
+	EXYNOS5_GPIO_Y34,
+	EXYNOS5_GPIO_Y35,
+	EXYNOS5_GPIO_Y36,
+	EXYNOS5_GPIO_Y37,
+	EXYNOS5_GPIO_Y40,
+	EXYNOS5_GPIO_Y41,
+	EXYNOS5_GPIO_Y42,
+	EXYNOS5_GPIO_Y43,
+	EXYNOS5_GPIO_Y44,
+	EXYNOS5_GPIO_Y45,
+	EXYNOS5_GPIO_Y46,
+	EXYNOS5_GPIO_Y47,
+	EXYNOS5_GPIO_Y50,
+	EXYNOS5_GPIO_Y51,
+	EXYNOS5_GPIO_Y52,
+	EXYNOS5_GPIO_Y53,
+	EXYNOS5_GPIO_Y54,
+	EXYNOS5_GPIO_Y55,
+	EXYNOS5_GPIO_Y56,
+	EXYNOS5_GPIO_Y57,
+	EXYNOS5_GPIO_Y60,
+	EXYNOS5_GPIO_Y61,
+	EXYNOS5_GPIO_Y62,
+	EXYNOS5_GPIO_Y63,
+	EXYNOS5_GPIO_Y64,
+	EXYNOS5_GPIO_Y65,
+	EXYNOS5_GPIO_Y66,
+	EXYNOS5_GPIO_Y67,
+
+	/* GPIO_PART2_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_1,
+	EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1,
+	EXYNOS5_GPIO_C41,
+	EXYNOS5_GPIO_C42,
+	EXYNOS5_GPIO_C43,
+	EXYNOS5_GPIO_C44,
+	EXYNOS5_GPIO_C45,
+	EXYNOS5_GPIO_C46,
+	EXYNOS5_GPIO_C47,
+
+	/* GPIO_PART3_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_2,
+	EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2,
+	EXYNOS5_GPIO_X01,
+	EXYNOS5_GPIO_X02,
+	EXYNOS5_GPIO_X03,
+	EXYNOS5_GPIO_X04,
+	EXYNOS5_GPIO_X05,
+	EXYNOS5_GPIO_X06,
+	EXYNOS5_GPIO_X07,
+	EXYNOS5_GPIO_X10,
+	EXYNOS5_GPIO_X11,
+	EXYNOS5_GPIO_X12,
+	EXYNOS5_GPIO_X13,
+	EXYNOS5_GPIO_X14,
+	EXYNOS5_GPIO_X15,
+	EXYNOS5_GPIO_X16,
+	EXYNOS5_GPIO_X17,
+	EXYNOS5_GPIO_X20,
+	EXYNOS5_GPIO_X21,
+	EXYNOS5_GPIO_X22,
+	EXYNOS5_GPIO_X23,
+	EXYNOS5_GPIO_X24,
+	EXYNOS5_GPIO_X25,
+	EXYNOS5_GPIO_X26,
+	EXYNOS5_GPIO_X27,
+	EXYNOS5_GPIO_X30,
+	EXYNOS5_GPIO_X31,
+	EXYNOS5_GPIO_X32,
+	EXYNOS5_GPIO_X33,
+	EXYNOS5_GPIO_X34,
+	EXYNOS5_GPIO_X35,
+	EXYNOS5_GPIO_X36,
+	EXYNOS5_GPIO_X37,
+
+	/* GPIO_PART4_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_3,
+	EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3,
+	EXYNOS5_GPIO_E01,
+	EXYNOS5_GPIO_E02,
+	EXYNOS5_GPIO_E03,
+	EXYNOS5_GPIO_E04,
+	EXYNOS5_GPIO_E05,
+	EXYNOS5_GPIO_E06,
+	EXYNOS5_GPIO_E07,
+	EXYNOS5_GPIO_E10,
+	EXYNOS5_GPIO_E11,
+	EXYNOS5_GPIO_E12,
+	EXYNOS5_GPIO_E13,
+	EXYNOS5_GPIO_E14,
+	EXYNOS5_GPIO_E15,
+	EXYNOS5_GPIO_E16,
+	EXYNOS5_GPIO_E17,
+	EXYNOS5_GPIO_F00,
+	EXYNOS5_GPIO_F01,
+	EXYNOS5_GPIO_F02,
+	EXYNOS5_GPIO_F03,
+	EXYNOS5_GPIO_F04,
+	EXYNOS5_GPIO_F05,
+	EXYNOS5_GPIO_F06,
+	EXYNOS5_GPIO_F07,
+	EXYNOS5_GPIO_F10,
+	EXYNOS5_GPIO_F11,
+	EXYNOS5_GPIO_F12,
+	EXYNOS5_GPIO_F13,
+	EXYNOS5_GPIO_F14,
+	EXYNOS5_GPIO_F15,
+	EXYNOS5_GPIO_F16,
+	EXYNOS5_GPIO_F17,
+	EXYNOS5_GPIO_G00,
+	EXYNOS5_GPIO_G01,
+	EXYNOS5_GPIO_G02,
+	EXYNOS5_GPIO_G03,
+	EXYNOS5_GPIO_G04,
+	EXYNOS5_GPIO_G05,
+	EXYNOS5_GPIO_G06,
+	EXYNOS5_GPIO_G07,
+	EXYNOS5_GPIO_G10,
+	EXYNOS5_GPIO_G11,
+	EXYNOS5_GPIO_G12,
+	EXYNOS5_GPIO_G13,
+	EXYNOS5_GPIO_G14,
+	EXYNOS5_GPIO_G15,
+	EXYNOS5_GPIO_G16,
+	EXYNOS5_GPIO_G17,
+	EXYNOS5_GPIO_G20,
+	EXYNOS5_GPIO_G21,
+	EXYNOS5_GPIO_G22,
+	EXYNOS5_GPIO_G23,
+	EXYNOS5_GPIO_G24,
+	EXYNOS5_GPIO_G25,
+	EXYNOS5_GPIO_G26,
+	EXYNOS5_GPIO_G27,
+	EXYNOS5_GPIO_H00,
+	EXYNOS5_GPIO_H01,
+	EXYNOS5_GPIO_H02,
+	EXYNOS5_GPIO_H03,
+	EXYNOS5_GPIO_H04,
+	EXYNOS5_GPIO_H05,
+	EXYNOS5_GPIO_H06,
+	EXYNOS5_GPIO_H07,
+	EXYNOS5_GPIO_H10,
+	EXYNOS5_GPIO_H11,
+	EXYNOS5_GPIO_H12,
+	EXYNOS5_GPIO_H13,
+	EXYNOS5_GPIO_H14,
+	EXYNOS5_GPIO_H15,
+	EXYNOS5_GPIO_H16,
+	EXYNOS5_GPIO_H17,
+
+	/* GPIO_PART4_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_4,
+	EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4,
+	EXYNOS5_GPIO_V01,
+	EXYNOS5_GPIO_V02,
+	EXYNOS5_GPIO_V03,
+	EXYNOS5_GPIO_V04,
+	EXYNOS5_GPIO_V05,
+	EXYNOS5_GPIO_V06,
+	EXYNOS5_GPIO_V07,
+	EXYNOS5_GPIO_V10,
+	EXYNOS5_GPIO_V11,
+	EXYNOS5_GPIO_V12,
+	EXYNOS5_GPIO_V13,
+	EXYNOS5_GPIO_V14,
+	EXYNOS5_GPIO_V15,
+	EXYNOS5_GPIO_V16,
+	EXYNOS5_GPIO_V17,
+
+	/* GPIO_PART5_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_5,
+	EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5,
+	EXYNOS5_GPIO_V21,
+	EXYNOS5_GPIO_V22,
+	EXYNOS5_GPIO_V23,
+	EXYNOS5_GPIO_V24,
+	EXYNOS5_GPIO_V25,
+	EXYNOS5_GPIO_V26,
+	EXYNOS5_GPIO_V27,
+	EXYNOS5_GPIO_V30,
+	EXYNOS5_GPIO_V31,
+	EXYNOS5_GPIO_V32,
+	EXYNOS5_GPIO_V33,
+	EXYNOS5_GPIO_V34,
+	EXYNOS5_GPIO_V35,
+	EXYNOS5_GPIO_V36,
+	EXYNOS5_GPIO_V37,
+
+	/* GPIO_PART6_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_6,
+	EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6,
+	EXYNOS5_GPIO_V41,
+	EXYNOS5_GPIO_V42,
+	EXYNOS5_GPIO_V43,
+	EXYNOS5_GPIO_V44,
+	EXYNOS5_GPIO_V45,
+	EXYNOS5_GPIO_V46,
+	EXYNOS5_GPIO_V47,
+
+	/* GPIO_PART6_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_7,
+	EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7,
+	EXYNOS5_GPIO_Z1,
+	EXYNOS5_GPIO_Z2,
+	EXYNOS5_GPIO_Z3,
+	EXYNOS5_GPIO_Z4,
+	EXYNOS5_GPIO_Z5,
+	EXYNOS5_GPIO_Z6,
+	EXYNOS5_GPIO_MAX_PORT
+};
+
 static inline unsigned int s5p_gpio_base(int nr)
 {
 	if (cpu_is_exynos5()) {
@@ -311,6 +667,12 @@  static inline unsigned int s5p_gpio_part_max(int nr)
 
 	return 0;
 }
+
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_pull(int gpio, int mode);
+void gpio_set_drv(int gpio, int mode);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_set_value(unsigned gpio, int value);
 #endif
 
 /* Pin configurations */
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 217c6df..f58237f 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -73,11 +73,8 @@  static void boot_temp_check(void)
 #ifdef CONFIG_USB_EHCI_EXYNOS
 int board_usb_vbus_init(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable VBUS power switch */
-	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+	gpio_direction_output(EXYNOS5_GPIO_X26, 1);
 
 	/* VBUS turn ON time */
 	mdelay(3);
@@ -89,12 +86,9 @@  int board_usb_vbus_init(void)
 #ifdef CONFIG_SOUND_MAX98095
 static void  board_enable_audio_codec(void)
 {
-	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
-						samsung_get_base_gpio_part1();
-
 	/* Enable MAX98095 Codec */
-	s5p_gpio_direction_output(&gpio1->x1, 7, 1);
-	s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+	gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+	gpio_set_pull(EXYNOS5_GPIO_X17, GPIO_PULL_NONE);
 }
 #endif
 
@@ -456,19 +450,17 @@  int board_early_init_f(void)
 #ifdef CONFIG_LCD
 void cfg_lcd_gpio(void)
 {
-	struct exynos5_gpio_part1 *gpio1 =
-		(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 
 	/* For Backlight */
-	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_B20, GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 
 	/* LCD power on */
-	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
-	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+	gpio_cfg_pin(EXYNOS5_GPIO_X15, GPIO_OUTPUT);
+	gpio_set_value(EXYNOS5_GPIO_X15, 1);
 
 	/* Set Hotplug detect for DP */
-	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+	gpio_cfg_pin(EXYNOS5_GPIO_X07, GPIO_FUNC(0x3));
 }
 
 vidinfo_t panel_info = {
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index 656bf4a..1b882cb 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -36,6 +36,27 @@ 
 #define RATE_MASK(x)		(0x1 << (x + 16))
 #define RATE_SET(x)		(0x1 << (x + 16))
 
+
+struct gpio_info {
+	unsigned int reg_addr;	/* Address of register for this part */
+	unsigned int max_gpio;	/* Maximum GPIO in this part */
+};
+
+#ifdef CONFIG_EXYNOS5
+static const struct gpio_info gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {
+	{ EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
+	{ EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
+	{ EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
+	{ EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
+	{ EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
+	{ EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
+	{ EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
+};
+
+#define HAVE_GENERIC_GPIO
+#endif
+
 void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
 {
 	unsigned int value;
@@ -141,7 +162,30 @@  void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
 
 	writel(value, &bank->drv);
 }
-
+#ifdef HAVE_GENERIC_GPIO
+static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
+{
+	const struct gpio_info *data;
+	unsigned int upto;
+	int i;
+
+	for (i = upto = 0, data = gpio_data; i < EXYNOS5_GPIO_NUM_PARTS;
+			i++, upto = data->max_gpio, data++) {
+		debug("i=%d, upto=%d\n", i, upto);
+		if (gpio < data->max_gpio) {
+			struct s5p_gpio_bank *bank;
+			bank = (struct s5p_gpio_bank *)data->reg_addr;
+			bank += (gpio - upto) / GPIO_PER_BANK;
+			debug("   gpio=%d, bank=%p\n", gpio, bank);
+			return bank;
+		}
+	}
+#ifndef CONFIG_SPL_BUILD
+	assert(gpio < EXYNOS5_GPIO_MAX_PORT);	/* ...which it will not be */
+#endif
+	return NULL;
+}
+#else
 struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 {
 	int bank;
@@ -151,6 +195,7 @@  struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio)
 	bank *= sizeof(struct s5p_gpio_bank);
 	return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank);
 }
+#endif
 
 int s5p_gpio_get_pin(unsigned gpio)
 {
@@ -196,3 +241,21 @@  int gpio_set_value(unsigned gpio, int value)
 
 	return 0;
 }
+
+void gpio_set_pull(int gpio, int mode)
+{
+	s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
+			s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_set_drv(int gpio, int mode)
+{
+	s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
+			s5p_gpio_get_pin(gpio), mode);
+}
+
+void gpio_cfg_pin(int gpio, int cfg)
+{
+	s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
+			s5p_gpio_get_pin(gpio), cfg);
+}