From patchwork Thu Mar 21 02:55:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Walter Lee X-Patchwork-Id: 229539 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id F20A82C00A5 for ; Thu, 21 Mar 2013 13:56:15 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:reply-to:mime-version:content-type; q=dns; s=default; b=EvarfOZeQ1Naw9ekK/rMPtbrI2SSlxrmc7Fmd7XfkoV rTurnyiU6nmOLokm4tryVqA4FY6nSjFg78VSV5eIAIaWfUX6JLVKG0QSPomPNx00 f1MqVZq7JKzrp+ZDNMLVoDK0gueKuGiA+EGxlUINDwImLksBLv7yQUMEzMar62Mg = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:from:to:subject:reply-to:mime-version:content-type; s=default; bh=nyPy6zEvvOG+wRZhOGsZg5z8VDc=; b=CpohFvd6eO8gZWVG/ GAS+x51Q/mjnoP5mASNFKOdZpfj2DWQoug4Psxh5mae67vTx/p3stN6aSZJzwxZJ DYQYGx0E7bztiH19/Ut5899WvwX8M4lUBs6ipdvtSpu03vdoq0dvjOV2e73w/PRe LzCApnK3uO7CgcRB4pU5sMFlVM= Received: (qmail 20218 invoked by alias); 21 Mar 2013 02:56:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20193 invoked by uid 89); 21 Mar 2013 02:55:59 -0000 X-Spam-SWARE-Status: No, score=-3.2 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.1 Received: from usmamail.tilera.com (HELO USMAMAIL.TILERA.COM) (12.216.194.151) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Thu, 21 Mar 2013 02:55:57 +0000 Received: from farm-0001.internal.tilera.com (10.2.0.31) by USMAEXCH2.tad.internal.tilera.com (10.3.0.33) with Microsoft SMTP Server (TLS) id 14.0.722.0; Wed, 20 Mar 2013 22:55:54 -0400 Received: (from walt@localhost) by farm-0001.internal.tilera.com (8.14.4/8.12.11/Submit) id r2L2ts8A018821; Wed, 20 Mar 2013 22:55:54 -0400 Date: Wed, 20 Mar 2013 22:55:54 -0400 Message-ID: <201303210255.r2L2ts8A018821@farm-0001.internal.tilera.com> From: Walter Lee To: Subject: [committed] TILE-Gx: add atomic test and set pattern Reply-To: Walter Lee MIME-Version: 1.0 This patch adds an atomic test and set pattern on tilegx. Without this pattern, libatomic currently fails to build on tilegx. Do I need permission to backport this to the 4.8 branch? Thanks, Walter * config/tilegx/sync.md (atomic_test_and_set): New pattern. Index: gcc/config/tilegx/sync.md =================================================================== --- gcc/config/tilegx/sync.md (revision 196804) +++ gcc/config/tilegx/sync.md (working copy) @@ -162,3 +162,49 @@ tilegx_post_atomic_barrier (model); DONE; }) + + +(define_expand "atomic_test_and_set" + [(match_operand:QI 0 "register_operand" "") ;; bool output + (match_operand:QI 1 "nonautoincmem_operand" "+U") ;; memory + (match_operand:SI 2 "const_int_operand" "")] ;; model + "" +{ + rtx addr, aligned_addr, aligned_mem, offset, word, shmt; + rtx tmp0, tmp1; + rtx result = operands[0]; + rtx mem = operands[1]; + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + + addr = force_reg (Pmode, XEXP (mem, 0)); + + aligned_addr = gen_reg_rtx (Pmode); + emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-8))); + + aligned_mem = change_address (mem, DImode, aligned_addr); + set_mem_alias_set (aligned_mem, 0); + + offset = gen_reg_rtx (DImode); + emit_move_insn (offset, gen_rtx_AND (DImode, gen_lowpart (DImode, addr), + GEN_INT (7))); + + tmp0 = gen_reg_rtx (DImode); + emit_move_insn (tmp0, GEN_INT (1)); + + shmt = gen_reg_rtx (DImode); + emit_move_insn (shmt, gen_rtx_ASHIFT (DImode, offset, GEN_INT (3))); + + word = gen_reg_rtx (DImode); + emit_move_insn (word, gen_rtx_ASHIFT (DImode, tmp0, + gen_lowpart (SImode, shmt))); + + tmp1 = gen_reg_rtx (DImode); + tilegx_pre_atomic_barrier (model); + emit_insn (gen_atomic_fetch_or_baredi (tmp1, aligned_mem, word)); + tilegx_post_atomic_barrier (model); + + emit_move_insn (gen_lowpart (DImode, result), + gen_rtx_LSHIFTRT (DImode, tmp1, + gen_lowpart (SImode, shmt))); + DONE; +})