From patchwork Wed Mar 20 15:38:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Porter X-Patchwork-Id: 229418 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F27722C00AA for ; Thu, 21 Mar 2013 02:37:41 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E1FC04A041; Wed, 20 Mar 2013 16:37:37 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nNdBJjeEKFGy; Wed, 20 Mar 2013 16:37:37 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 532084A046; Wed, 20 Mar 2013 16:37:22 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 10D744A03A for ; Wed, 20 Mar 2013 16:37:06 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Pn1JkdK6Ky-p for ; Wed, 20 Mar 2013 16:37:03 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ie0-f181.google.com (mail-ie0-f181.google.com [209.85.223.181]) by theia.denx.de (Postfix) with ESMTPS id 8DC054A02F for ; Wed, 20 Mar 2013 16:37:00 +0100 (CET) Received: by mail-ie0-f181.google.com with SMTP id 17so2155522iea.40 for ; Wed, 20 Mar 2013 08:36:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=mj8BAaXfQQpmZiq436QYF9yyNTHnVfDug91cKy+j3bM=; b=SIod0I1d5evTSHV9/0jA/sqa1LCh/atP6NDeOylibKZdb5gyeIZPZOAhsi5LiCrT6t RD6XRW9Rm1cws6fb+o+R3r0g+5THMuXV1iBFkZ7tg++3bL/efrQdasP6kgmemaniXuFG URj6y/v5AlzAK+pnXBpo6lVV0ScsQ3k+Gzp6mDgBhChecCwL0tUZac2YZ64OfRHP0eUG jNfPi5tDft+xL2da70go/yhlxUy5E4Jp1FAmyYQZpC9U35x4qbRUQ+pgpryWMMnjOhzX QHPiQxfJU+PZJjb7z9Yc1EdJOj2VmKrcjG2jxUCs+BHznFLcNqlRWZeaMzWETc8YQJ1P 1vIw== X-Received: by 10.50.193.200 with SMTP id hq8mr1790290igc.101.1363793817032; Wed, 20 Mar 2013 08:36:57 -0700 (PDT) Received: from beef.ohporter.com (cpe-98-27-254-98.neo.res.rr.com. [98.27.254.98]) by mx.google.com with ESMTPS id wn10sm5513244igb.2.2013.03.20.08.36.56 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 20 Mar 2013 08:36:56 -0700 (PDT) From: Matt Porter To: U-Boot Mailing List Date: Wed, 20 Mar 2013 11:38:11 -0400 Message-Id: <1363793894-1400-2-git-send-email-mporter@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1363793894-1400-1-git-send-email-mporter@ti.com> References: <1363793894-1400-1-git-send-email-mporter@ti.com> Cc: Tom Rini Subject: [U-Boot] [PATCH v2 1/4] am33xx: add pll and clock support for TI814x CPSW X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Enables required PLLs and clocks for CPSW on TI814x. Signed-off-by: Matt Porter Reviewed-by: Tom Rini --- v2: improved sata pll comment and added defines for magic values --- arch/arm/cpu/armv7/am33xx/clock_ti814x.c | 103 +++++++++++++++++++- arch/arm/include/asm/arch-am33xx/hardware_ti814x.h | 1 + board/ti/ti814x/evm.c | 3 + 3 files changed, 105 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c index cb4210f..8b2878d 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -109,6 +109,8 @@ struct ad_pll { #define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) /* PRCM */ +#define ENET_CLKCTRL_CMPL 0x30000 + #define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) struct cm_def { @@ -183,7 +185,7 @@ struct cm_alwon { unsigned int resv5[2]; unsigned int gpmcclkctrl; unsigned int ethernet0clkctrl; - unsigned int resv6[1]; + unsigned int ethernet1clkctrl; unsigned int mpuclkctrl; unsigned int debugssclkctrl; unsigned int l3clkctrl; @@ -203,9 +205,67 @@ struct cm_alwon { unsigned int custefuseclkctrl; }; +#define SATA_PLL_BASE (CTRL_BASE + 0x0720) + +struct sata_pll { + unsigned int pllcfg0; + unsigned int pllcfg1; + unsigned int pllcfg2; + unsigned int pllcfg3; + unsigned int pllcfg4; + unsigned int pllstatus; + unsigned int rxstatus; + unsigned int txstatus; + unsigned int testcfg; +}; + +#define SEL_IN_FREQ (0x1 << 31) +#define DIGCLRZ (0x1 << 30) +#define ENDIGLDO (0x1 << 4) +#define APLL_CP_CURR (0x1 << 3) +#define ENBGSC_REF (0x1 << 2) +#define ENPLLLDO (0x1 << 1) +#define ENPLL (0x1 << 0) + +#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF) +#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF) +#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO) +#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \ + ENPLLLDO | ENPLL) + +#define PLL_LOCK (0x1 << 0) + +#define ENSATAMODE (0x1 << 31) +#define PLLREFSEL (0x1 << 30) +#define MDIVINT (0x4b << 18) +#define EN_CLKAUX (0x1 << 5) +#define EN_CLK125M (0x1 << 4) +#define EN_CLK100M (0x1 << 3) +#define EN_CLK50M (0x1 << 2) + +#define SATA_PLLCFG1 (ENSATAMODE | \ + PLLREFSEL | \ + MDIVINT | \ + EN_CLKAUX | \ + EN_CLK125M | \ + EN_CLK100M | \ + EN_CLK50M) + +#define DIGLDO_EN_CAPLESSMODE (0x1 << 22) +#define PLLDO_EN_LDO_STABLE (0x1 << 11) +#define PLLDO_EN_BUF_CUR (0x1 << 7) +#define PLLDO_EN_LP (0x1 << 6) +#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1) + +#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \ + PLLDO_EN_LDO_STABLE | \ + PLLDO_EN_BUF_CUR | \ + PLLDO_EN_LP | \ + PLLDO_CTRL_TRIM_1_4V) const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; +const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; /* * Enable the peripheral clock for required peripherals @@ -221,6 +281,15 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) ; + + /* Ethernet */ + writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); + writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); + while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0) + ; + writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); + while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) + ; } /* @@ -365,6 +434,35 @@ void ddr_pll_config(unsigned int ddrpll_m) pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); } +void sata_pll_config(void) +{ + /* + * This sequence for configuring the SATA PLL + * resident in the control module is documented + * in TI8148 TRM section 21.3.1 + */ + writel(SATA_PLLCFG1, &spll->pllcfg1); + udelay(50); + + writel(SATA_PLLCFG3, &spll->pllcfg3); + udelay(50); + + writel(SATA_PLLCFG0_1, &spll->pllcfg0); + udelay(50); + + writel(SATA_PLLCFG0_2, &spll->pllcfg0); + udelay(50); + + writel(SATA_PLLCFG0_3, &spll->pllcfg0); + udelay(50); + + writel(SATA_PLLCFG0_4, &spll->pllcfg0); + udelay(50); + + while (((readl(&spll->pllstatus) & PLL_LOCK) == 0)) + ; +} + void enable_emif_clocks(void) {}; void enable_dmm_clocks(void) @@ -397,9 +495,10 @@ void pll_init() /* Enable the control module */ writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); + /* Configure PLLs */ mpu_pll_config(); - l3_pll_config(); + sata_pll_config(); /* Enable the required peripherals */ enable_per_clocks(); diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h index a950ac3..8f9315c 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -29,6 +29,7 @@ /* Control Module Base Address */ #define CTRL_BASE 0x48140000 +#define CTRL_DEVICE_BASE 0x48140600 /* PRCM Base Address */ #define PRCM_BASE 0x48180000 diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index acc18fb..8513220 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -151,6 +151,9 @@ void s_init(void) */ wdt_disable(); + /* Enable timer */ + timer_init(); + /* Setup the PLLs and the clocks for the peripherals */ pll_init();