From patchwork Mon Mar 18 23:25:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 228835 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0D3972C00A7 for ; Tue, 19 Mar 2013 10:26:40 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C07A34A03E; Tue, 19 Mar 2013 00:26:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pWnGAFH+EzdU; Tue, 19 Mar 2013 00:26:26 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C9E4E4A049; Tue, 19 Mar 2013 00:26:20 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 87CE94A036 for ; Tue, 19 Mar 2013 00:26:17 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id spQ+0AZJACua for ; Tue, 19 Mar 2013 00:26:16 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f51.google.com (mail-pb0-f51.google.com [209.85.160.51]) by theia.denx.de (Postfix) with ESMTPS id 03C3F4A033 for ; Tue, 19 Mar 2013 00:26:05 +0100 (CET) Received: by mail-pb0-f51.google.com with SMTP id un15so6809258pbc.38 for ; Mon, 18 Mar 2013 16:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-nvconfidentiality; bh=pa6yA1ICPa8uYI1aYf5nON9NG7M1xmWIFELTp+oxfy4=; b=LaAUNgnGUB7G2pkuBBkFepnEKWNDBNACTY90Ok4/FXsazuKOSIjN3CO3alIAkKlBph JuR2pYnJm8ZCEIlL+t/B7lTpI6VzPxvEBw4IgGlR5srbXC0KsiiMVM5gwd+xobe7VAzb /+UuHV2o+Pk7qIwi2KCEYGKiJYvKug+SBu5GblPXwGI8AES0oJ+uqA9J/CUhkMrlwzbq +fapwD7GXu9xJdhPnhpOR6p2T/zT21xsf8KSvp4bcD9+AwJGsY4JqXMDYJN3N2CY6VK9 0gtpnyasFRBPJY0/KTBWMqtNQ1JjZKo+5raOB6O4FKS9AHWJSBudZWqaisHnjM3nGydO LkfA== X-Received: by 10.68.204.164 with SMTP id kz4mr35419748pbc.158.1363649163480; Mon, 18 Mar 2013 16:26:03 -0700 (PDT) Received: from tom-ubuntu64.nvidia.com (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id zm1sm21733930pbc.26.2013.03.18.16.26.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 18 Mar 2013 16:26:02 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Mon, 18 Mar 2013 16:25:34 -0700 Message-Id: <1363649136-23155-3-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1363649136-23155-1-git-send-email-twarren@nvidia.com> References: <1363649136-23155-1-git-send-email-twarren@nvidia.com> X-NVConfidentiality: public Cc: swarren@nvidia.com, afleming@freescale.com, Tom Warren , twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH v2 2/4] Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config table X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup before the MMC driver is added. Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- v2: Remove SDIOCFG_HSM define, unused. arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 6 ++++++ board/nvidia/dalmore/dalmore.c | 4 ++++ board/nvidia/dalmore/pinmux-config-dalmore.h | 6 ++++++ 3 files changed, 16 insertions(+) diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h index 1ef1a14..41ce677 100644 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -74,4 +74,10 @@ struct apb_misc_gp_ctlr { u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ }; +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + #endif /* _TEGRA114_GP_PADCTRL_H_ */ diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index 2020a5f..7449b5b 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -16,6 +16,7 @@ #include #include +#include #include "pinmux-config-dalmore.h" /* @@ -32,4 +33,7 @@ void pinmux_init(void) pinmux_config_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl)); } diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 3ef6f4e..8c05a15 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -361,4 +361,10 @@ static struct pingroup_config tegra114_pinmux_set_nontristate[] = { DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), }; + +static struct padctrl_config dalmore_padctrl[] = { + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), +}; #endif /* PINMUX_CONFIG_COMMON_H */