From patchwork Mon Mar 18 08:09:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 228383 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 275C82C009B for ; Mon, 18 Mar 2013 19:10:21 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751862Ab3CRIKS (ORCPT ); Mon, 18 Mar 2013 04:10:18 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:1840 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751979Ab3CRIKQ (ORCPT ); Mon, 18 Mar 2013 04:10:16 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Mon, 18 Mar 2013 01:10:09 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 18 Mar 2013 01:10:11 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 18 Mar 2013 01:10:11 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.298.1; Mon, 18 Mar 2013 01:10:11 -0700 From: Joseph Lo To: Stephen Warren CC: , , Joseph Lo Subject: [PATCH V2 2/3] ARM: tegra: get PMC clock source from DT Date: Mon, 18 Mar 2013 16:09:58 +0800 Message-ID: <1363594199-10974-3-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1363594199-10974-1-git-send-email-josephl@nvidia.com> References: <1363594199-10974-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The clock source of PMC should be PCLK and gotten from DT. Signed-off-by: Joseph Lo --- V2: * new in this change --- arch/arm/mach-tegra/common.c | 2 +- arch/arm/mach-tegra/pmc.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index f0315c9..b02ebe7 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -61,6 +61,7 @@ u32 tegra_uart_config[4] = { void __init tegra_dt_init_irq(void) { tegra_clocks_init(); + tegra_pmc_init(); tegra_init_irq(); irqchip_init(); } @@ -100,7 +101,6 @@ void __init tegra_init_early(void) tegra_apb_io_init(); tegra_init_fuse(); tegra_init_cache(); - tegra_pmc_init(); tegra_powergate_init(); tegra_hotplug_init(); } diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index b30e921..05259fd 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -19,6 +19,7 @@ #include #include #include +#include #define PMC_CTRL 0x0 #define PMC_CTRL_INTR_LOW (1 << 17) @@ -43,6 +44,7 @@ static DEFINE_SPINLOCK(tegra_powergate_lock); static void __iomem *tegra_pmc_base; static bool tegra_pmc_invert_interrupt; +static struct clk *tegra_pclk; static inline u32 tegra_pmc_readl(u32 reg) { @@ -151,6 +153,8 @@ static void tegra_pmc_parse_dt(void) tegra_pmc_invert_interrupt = of_property_read_bool(np, "nvidia,invert-interrupt"); + tegra_pclk = of_clk_get(np, 0); + WARN_ON_ONCE(IS_ERR(tegra_pclk)); } void __init tegra_pmc_init(void)