From patchwork Fri Mar 15 13:15:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuo-Jung Su X-Patchwork-Id: 227998 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A06B12C0089 for ; Sat, 16 Mar 2013 00:55:30 +1100 (EST) Received: from localhost ([::1]:52173 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UGUYT-0006PN-Ui for incoming@patchwork.ozlabs.org; Fri, 15 Mar 2013 09:20:17 -0400 Received: from eggs.gnu.org ([208.118.235.92]:34172) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UGUUD-0008VK-8G for qemu-devel@nongnu.org; Fri, 15 Mar 2013 09:16:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UGUU7-00050O-Dt for qemu-devel@nongnu.org; Fri, 15 Mar 2013 09:15:52 -0400 Received: from mail-pb0-f50.google.com ([209.85.160.50]:54753) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UGUU7-00050B-5G for qemu-devel@nongnu.org; Fri, 15 Mar 2013 09:15:47 -0400 Received: by mail-pb0-f50.google.com with SMTP id up1so3772625pbc.23 for ; Fri, 15 Mar 2013 06:15:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=xOMujBE9h54zhsnqR73xQ2dD7k6Fry8+tCmasjVwZLs=; b=HaDKS+qe7JiRxQ8dWLmYR4pFXlWo0HCtIvuthcauXKobUg4wwxvjUDo/L+4TnmpVLE 5lA3AkA+NpZcSf5rxTh4XgaRPWSQkzRlxhlGVljdcPqrG22DyFhAbGOg7xFRu6ymLRVY YLsY/V69iXOOdMXTfcPm8/a+jEJV34QZ6aVRgGy4pV66CbDF6YtuEJ+8QclWnBNBGM/K aOvT105ITog1v+PYZxQ9EYC+Aiaryj7gL36BwWwPCiYHC7IbK5Qlup8TVyDnYeYhoO82 faka15Y84y21OwP09M4T/jrz+qkj893AXAzTuUwW74XSCqBNRKYsiPB/b60WSSQdjrTL LZAg== X-Received: by 10.68.39.129 with SMTP id p1mr16232363pbk.19.1363353346524; Fri, 15 Mar 2013 06:15:46 -0700 (PDT) Received: from localhost.localdomain ([220.132.37.35]) by mx.google.com with ESMTPS id xr3sm8729551pbc.46.2013.03.15.06.15.43 (version=TLSv1 cipher=DES-CBC3-SHA bits=168/168); Fri, 15 Mar 2013 06:15:45 -0700 (PDT) From: Kuo-Jung Su To: qemu-devel@nongnu.org Date: Fri, 15 Mar 2013 21:15:16 +0800 Message-Id: <1363353336-11237-5-git-send-email-dantesu@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1363353336-11237-1-git-send-email-dantesu@gmail.com> References: <1363353336-11237-1-git-send-email-dantesu@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.160.50 Cc: Peter Maydell , i.mitsyanko@samsung.com, Blue Swirl , Paul Brook , Kuo-Jung Su , Andreas , fred.konrad@greensocs.com Subject: [Qemu-devel] [PATCH v8 04/24] hw/arm: add FTAHBC020 AHB controller support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Kuo-Jung Su It's used to perform AHB remap and QEMU RAM initialization when the SDRAM is initialized before AHB remap process activated. Signed-off-by: Kuo-Jung Su --- hw/arm/Makefile.objs | 1 + hw/arm/faraday_a369_soc.c | 10 +++ hw/arm/ftahbc020.c | 202 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 213 insertions(+) create mode 100644 hw/arm/ftahbc020.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 536d6cf..af36b01 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -38,3 +38,4 @@ obj-y += omap1.o omap2.o obj-y += faraday_a369.o faraday_a369_soc.o faraday_a369_scu.o \ faraday_a369_kpd.o obj-y += ftintc020.o +obj-y += ftahbc020.o diff --git a/hw/arm/faraday_a369_soc.c b/hw/arm/faraday_a369_soc.c index eab05dc..01b4395 100644 --- a/hw/arm/faraday_a369_soc.c +++ b/hw/arm/faraday_a369_soc.c @@ -70,6 +70,7 @@ static void a369soc_reset(DeviceState *ds) static void a369soc_device_init(FaradaySoCState *s) { + Error *local_errp = NULL; DriveInfo *dinfo; DeviceState *ds; qemu_irq *cpu_pic; @@ -148,6 +149,15 @@ a369soc_device_init(FaradaySoCState *s) /* ftkbc010 */ ds = sysbus_create_simple("a369.kpd", 0x92f00000, s->pic[21]); + + /* ftahbc020 */ + ds = sysbus_create_simple("ftahbc020", 0x94000000, NULL); + s->ahbc = ds; + object_property_set_link(OBJECT(ds), OBJECT(s), "soc", &local_errp); + if (local_errp) { + fprintf(stderr, "a369soc: Unable to set soc link for FTAHBC020\n"); + abort(); + } } static void a369soc_realize(DeviceState *dev, Error **errp) diff --git a/hw/arm/ftahbc020.c b/hw/arm/ftahbc020.c new file mode 100644 index 0000000..5681906 --- /dev/null +++ b/hw/arm/ftahbc020.c @@ -0,0 +1,202 @@ +/* + * Faraday AHB controller + * + * Copyright (c) 2012 Faraday Technology + * Written by Dante Su + * + * This code is licensed under GNU GPL v2+ + */ + +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "hw/devices.h" +#include "sysemu/sysemu.h" + +#include "faraday.h" + +#define REG_SLAVE(n) ((n) * 4) /* Slave config (base & size) */ +#define REG_PRIR 0x80 /* Priority register */ +#define REG_IDLECR 0x84 /* IDLE count register */ +#define REG_CR 0x88 /* Control register */ +#define REG_REVR 0x8c /* Revision register */ + +#define CR_REMAP 0x01 /* Enable AHB remap for slave 4 & 6 */ + +#define TYPE_FTAHBC020 "ftahbc020" + +typedef struct Ftahbc020State { + SysBusDevice busdev; + MemoryRegion iomem; + + FaradaySoCState *soc; + /* HW register cache */ + uint32_t cr; +} Ftahbc020State; + +#define FTAHBC020(obj) \ + OBJECT_CHECK(Ftahbc020State, obj, TYPE_FTAHBC020) + +static uint64_t +ftahbc020_mem_read(void *opaque, hwaddr addr, unsigned size) +{ + Ftahbc020State *s = FTAHBC020(opaque); + uint64_t ret = 0; + + switch (addr) { + /* slave address & window configuration */ + case REG_SLAVE(0) ... REG_SLAVE(3): + /* fall-through - skip slave4 */ + case REG_SLAVE(5): + /* fall-through - skip slave6 */ + case REG_SLAVE(7) ... REG_SLAVE(31): + ret = s->soc->ahb_slave[addr / 4]; + break; + case REG_SLAVE(4): + ret = s->soc->rom_base | (s->soc->ahb_slave[4] & 0x000f0000); + break; + case REG_SLAVE(6): + ret = s->soc->ram_base | (s->soc->ahb_slave[6] & 0x000f0000); + break; + /* control register */ + case REG_CR: + if (s->soc->ahb_remapped) { + s->cr |= CR_REMAP; + } + ret = s->cr; + break; + case REG_REVR: + ret = 0x00010301; /* rev. 1.3.1 */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "ftahbc020: undefined memory access@%#" HWADDR_PRIx "\n", addr); + break; + } + + return ret; +} + +static void +ftahbc020_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + Ftahbc020State *s = FTAHBC020(opaque); + + switch (addr) { + case REG_CR: /* control register */ + s->cr = (uint32_t)val; + if (s->soc->ahb_remapped && !(s->cr & CR_REMAP)) { + fprintf(stderr, "ftahbc020: Once AHB remap is enabled, " + "it could not be disabled!\n"); + abort(); + } + if (!s->soc->ahb_remapped && (s->cr & CR_REMAP)) { + /* Remap AHB slave 4 (ROM) & slave 6 (RAM) */ + /* 1. Remap RAM to base of ROM */ + s->soc->ram_base = s->soc->ahb_slave[4] & 0xfff00000; + /* 2. Remap ROM to base of ROM + size of RAM */ + s->soc->rom_base = s->soc->ram_base + + ((1 << extract32(s->soc->ahb_slave[6], 16, 4)) << 20); + /* 3. Update ROM memory map */ + sysbus_mmio_map(SYS_BUS_DEVICE(s->soc->rom), 0, s->soc->rom_base); + /* 4. Update RAM memory map if it has been initialized. */ + if (s->soc->ddr_inited) { + memory_region_del_subregion(s->soc->as, s->soc->ram); + memory_region_add_subregion(s->soc->as, s->soc->ram_base, + s->soc->ram); + } + s->soc->ahb_remapped = true; + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "ftahbc020: undefined memory access@%#" HWADDR_PRIx "\n", addr); + break; + } +} + +static const MemoryRegionOps mmio_ops = { + .read = ftahbc020_mem_read, + .write = ftahbc020_mem_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + } +}; + +static void ftahbc020_reset(DeviceState *ds) +{ + Ftahbc020State *s = FTAHBC020(SYS_BUS_DEVICE(ds)); + Error *local_errp = NULL; + + s->soc = FARADAY_SOC(object_property_get_link(OBJECT(s), + "soc", + &local_errp)); + if (local_errp) { + fprintf(stderr, "ftahbc020: Unable to get soc link\n"); + abort(); + } + + if (s->soc->ahb_remapped && !s->soc->bi) { + s->soc->rom_base = s->soc->ahb_slave[4] & 0xfff00000; + s->soc->ram_base = s->soc->ahb_slave[6] & 0xfff00000; + sysbus_mmio_map(SYS_BUS_DEVICE(s->soc->rom), 0, s->soc->rom_base); + s->soc->ahb_remapped = false; + } + + s->cr = 0; +} + +static void ftahbc020_realize(DeviceState *dev, Error **errp) +{ + Ftahbc020State *s = FTAHBC020(dev); + + memory_region_init_io(&s->iomem, + &mmio_ops, + s, + TYPE_FTAHBC020, + 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + + object_property_add_link(OBJECT(dev), + "soc", + TYPE_FARADAY_SOC, + (Object **) &s->soc, + errp); +} + +static const VMStateDescription vmstate_ftahbc020 = { + .name = TYPE_FTAHBC020, + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(cr, Ftahbc020State), + VMSTATE_END_OF_LIST(), + } +}; + +static void ftahbc020_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = TYPE_FTAHBC020; + dc->vmsd = &vmstate_ftahbc020; + dc->reset = ftahbc020_reset; + dc->realize = ftahbc020_realize; + dc->no_user = 1; +} + +static const TypeInfo ftahbc020_info = { + .name = TYPE_FTAHBC020, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Ftahbc020State), + .class_init = ftahbc020_class_init, +}; + +static void ftahbc020_register_types(void) +{ + type_register_static(&ftahbc020_info); +} + +type_init(ftahbc020_register_types)