From patchwork Fri Mar 15 12:29:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Saraswat X-Patchwork-Id: 227965 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 352922C0092 for ; Fri, 15 Mar 2013 23:09:56 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 648594A16C; Fri, 15 Mar 2013 13:09:54 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zA98GWrqiJAn; Fri, 15 Mar 2013 13:09:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B73044A17A; Fri, 15 Mar 2013 13:09:52 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 683494A17A for ; Fri, 15 Mar 2013 13:09:49 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PS9fY+B2xB2S for ; Fri, 15 Mar 2013 13:09:47 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by theia.denx.de (Postfix) with ESMTP id BD2B64A16C for ; Fri, 15 Mar 2013 13:09:45 +0100 (CET) Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MJP00BFFB3ZJK80@mailout4.samsung.com> for u-boot@lists.denx.de; Fri, 15 Mar 2013 21:09:39 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 22.95.20872.38F03415; Fri, 15 Mar 2013 21:09:39 +0900 (KST) X-AuditID: cbfee68d-b7f786d000005188-69-51430f83df16 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 3F.80.13494.38F03415; Fri, 15 Mar 2013 21:09:39 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MJP002S5B2TB020@mmp2.samsung.com>; Fri, 15 Mar 2013 21:09:39 +0900 (KST) From: Akshay Saraswat To: u-boot@lists.denx.de Date: Fri, 15 Mar 2013 08:29:09 -0400 Message-id: <1363350549-6282-1-git-send-email-akshay.s@samsung.com> X-Mailer: git-send-email 1.8.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsWyRsSkSreZ3znQYOJZeYvDz2Ispj44x2jx bcs2Rou3ezvZHVg81sxbw+gxu+Eii8fOWXfZPc7e2cEYwBLFZZOSmpNZllqkb5fAlbGy4wF7 wQrRihsvOpgaGBuEuhg5OSQETCTmHHzFDGGLSVy4t56ti5GLQ0hgKaPEoTm3WWCKzi1shUpM Z5R4MPEYI4TTyyTxdcthJpAqNgEdie1LvrOD2CICEhK/+q8ygtjMAg4S7xb0g8WFBVwlnr46 C2azCKhK3F83HWgqBwevgLPE5ef+EMvkJD7secQOMl9C4DGbxOqb66DqBSS+TT7EAlIvISAr sekA1NWSEgdX3GCZwCi4gJFhFaNoakFyQXFSepGhXnFibnFpXrpecn7uJkZgOJ7+96x3B+Pt A9aHGJOBxk1klhJNzgeGc15JvKGxmZGFqYmpsZG5pRlpwkrivGot1oFCAumJJanZqakFqUXx RaU5qcWHGJk4OKUaGJM5H5YZWQdUzH4qYdzzInZK2c+c+VN6jhfuuxY479XsO3XcPaGRt066 aW/32nvs3PKc3WbvzmRvmfeBKdz81Yu1PiJ7zHYlN9fxb9d+3Tov0Ov/1FeZtx/d/WJ6/cmZ 1ZlvDkRN4m2qnP/tbnnFde0E0771lxxP8Lw56eho4r3efDNvmIKR6nslluKMREMt5qLiRAB2 bBP9XQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrOIsWRmVeSWpSXmKPExsVy+t9jQd1mfudAg4kfxC0OP4uxmPrgHKPF ty3bGC3e7u1kd2DxWDNvDaPH7IaLLB47Z91l9zh7ZwdjAEtUA6NNRmpiSmqRQmpecn5KZl66 rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtBOJYWyxJxSoFBAYnGxkr4dpgmhIW66 FjCNEbq+IUFwPUYGaCBhDWPGyo4H7AUrRCtuvOhgamBsEOpi5OSQEDCROLewlQ3CFpO4cG89 kM3FISQwnVHiwcRjjBBOL5PE1y2HmUCq2AR0JLYv+c4OYosISEj86r/KCGIzCzhIvFvQDxYX FnCVePrqLJjNIqAqcX/ddKCpHBy8As4Sl5/7QyyTk/iw5xH7BEbuBYwMqxhFUwuSC4qT0nON 9IoTc4tL89L1kvNzNzGCg/2Z9A7GVQ0WhxgFOBiVeHgdHjoGCrEmlhVX5h5ilOBgVhLh/XjR KVCINyWxsiq1KD++qDQntfgQYzLQ8onMUqLJ+cBIzCuJNzQ2MTc1NrU0sTAxsyRNWEmc92Cr daCQQHpiSWp2ampBahHMFiYOTqkGRv17m8qm5QTL8aTcsBX1Fd3vPyXPwWVH+cZVD7/M883h ibLcwrB9HseCG8ccMienc+Wbvv2rFmI2/9S/H25TUyaVr16SwpP0MPuLmX/StdOeH6/u4YrZ 7yQk+CTn6ww9Fp1sMQM1ifgOhqLVtraLZtgZmM3lWcoqyWp8S6Ryr/IWqeAWlYnaSizFGYmG WsxFxYkAzqAxOroCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: alexei.fedorov@arm.com Subject: [U-Boot] [PATCH] Exynos: clock: Fix a bug in PLL lock check condition X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The condition for testing of PLL getting locked was incorrect. Rectify this error in this patch. Reported-by: Alexei Fedorov Signed-off-by: Hatim Ali Signed-off-by: Akshay Saraswat Acked-by: Simon Glass --- board/samsung/smdk5250/clock_init.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae5..baa3042 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -494,35 +494,35 @@ void system_clock_init() val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, arm_clk_ratio->apll_sdiv); writel(val, &clk->apll_con0); - while (readl(&clk->apll_con0) & APLL_CON0_LOCKED) + while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) ; /* Set MPLL */ writel(MPLL_CON1_VAL, &clk->mpll_con1); val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); writel(val, &clk->mpll_con0); - while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) + while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) ; /* Set BPLL */ writel(BPLL_CON1_VAL, &clk->bpll_con1); val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); writel(val, &clk->bpll_con0); - while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) + while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) ; /* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); writel(val, &clk->cpll_con0); - while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) + while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) ; /* Set GPLL */ writel(GPLL_CON1_VAL, &clk->gpll_con1); val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); writel(val, &clk->gpll_con0); - while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) + while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) ; /* Set EPLL */ @@ -530,7 +530,7 @@ void system_clock_init() writel(EPLL_CON1_VAL, &clk->epll_con1); val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); writel(val, &clk->epll_con0); - while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED) + while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) ; /* Set VPLL */ @@ -538,7 +538,7 @@ void system_clock_init() writel(VPLL_CON1_VAL, &clk->vpll_con1); val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); writel(val, &clk->vpll_con0); - while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) + while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) ; writel(CLK_SRC_CORE0_VAL, &clk->src_core0);