From patchwork Tue Mar 12 16:17:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 227074 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 84A122C0092 for ; Wed, 13 Mar 2013 03:18:57 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EDA084A277; Tue, 12 Mar 2013 17:18:54 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EsG-9A1MAqHb; Tue, 12 Mar 2013 17:18:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1F2424A253; Tue, 12 Mar 2013 17:18:41 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 535EF4A104 for ; Tue, 12 Mar 2013 17:18:30 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VpsbVHixCX5B for ; Tue, 12 Mar 2013 17:18:29 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f54.google.com (mail-pb0-f54.google.com [209.85.160.54]) by theia.denx.de (Postfix) with ESMTPS id 1FDD14A235 for ; Tue, 12 Mar 2013 17:18:27 +0100 (CET) Received: by mail-pb0-f54.google.com with SMTP id rr4so9534pbb.27 for ; Tue, 12 Mar 2013 09:18:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-nvconfidentiality; bh=zheV5/FCzqS7NKKAvi4i0fAPfKsb/xgw2Awsl91dLEA=; b=Iml1wpVRYBB7abFaJH7CactKh2kJNv3WsVwbgdVcZwqOj1AIaDT/Y267RijLz64LgY 3oExQHOA/Obd4qtc0m5yI1/EBbxd/w8l9hbcTcNLxab6pXX/B+QzDV3zqFegB6A2YFf7 SkwrE6UAzOFUtaFO/v54m9ZkGRTh3AdoGKf8PBxD9AgQup8F3bPHUaAKjCJVEg82IM+6 jRw8d4Vet1TdmWl+PXhZiunhDnkR/Ugm7DKxrVSDZ+EMHuFmSN4FRms7PAK7I5sXrmqR TEt0uSgU6hj/qm+ZsbX/IlsCEH8UiABHyqiiHVHFR+5XRBJX0LoqpLlH9Uy9SPzQPGhB 0d3Q== X-Received: by 10.68.177.162 with SMTP id cr2mr225655pbc.179.1363105106440; Tue, 12 Mar 2013 09:18:26 -0700 (PDT) Received: from localhost.localdomain (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id ql7sm10078177pbb.2.2013.03.12.09.18.23 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 12 Mar 2013 09:18:25 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Tue, 12 Mar 2013 09:17:09 -0700 Message-Id: <1363105031-30296-3-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1363105031-30296-1-git-send-email-twarren@nvidia.com> References: <1363105031-30296-1-git-send-email-twarren@nvidia.com> X-NVConfidentiality: public Cc: swarren@nvidia.com, afleming@freescale.com, Tom Warren , twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH 2/4] Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config table X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup before the MMC driver is added. Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra114/gp_padctrl.h | 7 +++++++ board/nvidia/dalmore/dalmore.c | 4 ++++ board/nvidia/dalmore/pinmux-config-dalmore.h | 2 ++ 3 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h index c538bdd..82c70cb 100644 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -56,4 +56,11 @@ struct apb_misc_gp_ctlr { u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ }; +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 +#define SDIOCFG_HSM 1 + #endif /* _TEGRA114_GP_PADCTRL_H_ */ diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index 2020a5f..7449b5b 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -16,6 +16,7 @@ #include #include +#include #include "pinmux-config-dalmore.h" /* @@ -32,4 +33,7 @@ void pinmux_init(void) pinmux_config_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl)); } diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index e6fe842..7af3f75 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -364,5 +364,7 @@ static struct pingroup_config tegra114_pinmux_set_nontristate[] = { static struct padctrl_config dalmore_padctrl[] = { /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, ENABLE), }; #endif /* PINMUX_CONFIG_COMMON_H */