From patchwork Tue Mar 12 10:31:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 226975 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9B87D2C0580 for ; Tue, 12 Mar 2013 22:52:19 +1100 (EST) Received: from localhost ([::1]:60097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFMe6-0003rc-RT for incoming@patchwork.ozlabs.org; Tue, 12 Mar 2013 06:41:26 -0400 Received: from eggs.gnu.org ([208.118.235.92]:44312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFMVO-0000KI-U6 for qemu-devel@nongnu.org; Tue, 12 Mar 2013 06:33:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UFMV5-0004ly-2A for qemu-devel@nongnu.org; Tue, 12 Mar 2013 06:32:26 -0400 Received: from ozlabs.org ([203.10.76.45]:45494) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFMV4-0004jx-FI; Tue, 12 Mar 2013 06:32:06 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 61EAB2C02B7; Tue, 12 Mar 2013 21:32:01 +1100 (EST) From: David Gibson To: agraf@suse.de Date: Tue, 12 Mar 2013 21:31:23 +1100 Message-Id: <1363084310-4115-22-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1363084310-4115-1-git-send-email-david@gibson.dropbear.id.au> References: <1363084310-4115-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 203.10.76.45 Cc: David Gibson , qemu-ppc@nongnu.org, afaerber@suse.de, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 21/48] mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, 64}() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org After previous work, ppc_hash{32,64}_get_physical_address() are almost trivial wrappers around get_segment{32,64}() which does nearly all the work of translating an address according to the hash mmu model. Therefore combine the two functions into one, under the better name of ppc_hash{32,64}_translate(). Signed-off-by: David Gibson --- target-ppc/mmu-hash32.c | 49 +++++++++++++++++++---------------------------- target-ppc/mmu-hash64.c | 37 +++++++++++++++-------------------- 2 files changed, 35 insertions(+), 51 deletions(-) diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 8001563..bc97834 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -376,8 +376,8 @@ static int find_pte32(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, return ret; } -static int get_segment32(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, - target_ulong eaddr, int rwx) +static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, + target_ulong eaddr, int rwx) { hwaddr hash; target_ulong vsid; @@ -385,6 +385,22 @@ static int get_segment32(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, int ret, ret2; target_ulong sr, pgidx; + /* 1. Handle real mode accesses */ + if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { + /* Translation is off */ + ctx->raddr = eaddr; + ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE; + return 0; + } + + /* 2. Check Block Address Translation entries (BATs) */ + if (env->nb_BATs != 0) { + ret = ppc_hash32_get_bat(env, ctx, eaddr, rwx); + if (ret == 0) { + return 0; + } + } + pr = msr_pr; sr = env->sr[eaddr >> 28]; @@ -521,38 +537,13 @@ static int get_segment32(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, return ret; } -static int ppc_hash32_get_physical_address(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, - target_ulong eaddr, int rwx) -{ - bool real_mode = (rwx == 2 && msr_ir == 0) - || (rwx != 2 && msr_dr == 0); - - if (real_mode) { - ctx->raddr = eaddr; - ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE; - return 0; - } else { - int ret = -1; - - /* Try to find a BAT */ - if (env->nb_BATs != 0) { - ret = ppc_hash32_get_bat(env, ctx, eaddr, rwx); - } - if (ret < 0) { - /* We didn't match any BAT entry or don't have BATs */ - ret = get_segment32(env, ctx, eaddr, rwx); - } - return ret; - } -} - hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr) { struct mmu_ctx_hash32 ctx; /* FIXME: Will not behave sanely for direct store segments, but * they're almost never used */ - if (unlikely(ppc_hash32_get_physical_address(env, &ctx, addr, 0) + if (unlikely(ppc_hash32_translate(env, &ctx, addr, 0) != 0)) { return -1; } @@ -566,7 +557,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx, struct mmu_ctx_hash32 ctx; int ret = 0; - ret = ppc_hash32_get_physical_address(env, &ctx, address, rwx); + ret = ppc_hash32_translate(env, &ctx, address, rwx); if (ret == 0) { tlb_set_page(env, address & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot, diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 407c6e6..9afc418 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -434,19 +434,28 @@ static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, return ret; } -static int get_segment64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, - target_ulong eaddr, int rwx) +static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, + target_ulong eaddr, int rwx) { hwaddr hash; target_ulong vsid; int pr, target_page_bits; int ret, ret2; - - pr = msr_pr; ppc_slb_t *slb; target_ulong pageaddr; int segment_bits; + /* 1. Handle real mode accesses */ + if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { + /* Translation is off */ + /* In real mode the top 4 effective address bits are ignored */ + ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; + ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE; + return 0; + } + + pr = msr_pr; + LOG_MMU("Check SLBs\n"); slb = slb_lookup(env, eaddr); if (!slb) { @@ -518,27 +527,11 @@ static int get_segment64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, return ret; } -static int ppc_hash64_get_physical_address(CPUPPCState *env, - struct mmu_ctx_hash64 *ctx, - target_ulong eaddr, int rwx) -{ - bool real_mode = (rwx == 2 && msr_ir == 0) - || (rwx != 2 && msr_dr == 0); - - if (real_mode) { - ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; - ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE; - return 0; - } else { - return get_segment64(env, ctx, eaddr, rwx); - } -} - hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr) { struct mmu_ctx_hash64 ctx; - if (unlikely(ppc_hash64_get_physical_address(env, &ctx, addr, 0) != 0)) { + if (unlikely(ppc_hash64_translate(env, &ctx, addr, 0) != 0)) { return -1; } @@ -551,7 +544,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rwx, struct mmu_ctx_hash64 ctx; int ret = 0; - ret = ppc_hash64_get_physical_address(env, &ctx, address, rwx); + ret = ppc_hash64_translate(env, &ctx, address, rwx); if (ret == 0) { tlb_set_page(env, address & TARGET_PAGE_MASK, ctx.raddr & TARGET_PAGE_MASK, ctx.prot,