From patchwork Tue Mar 12 10:31:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 226929 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CDBE72C0086 for ; Tue, 12 Mar 2013 22:06:30 +1100 (EST) Received: from localhost ([::1]:33839 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFMfA-0004x4-JI for incoming@patchwork.ozlabs.org; Tue, 12 Mar 2013 06:42:32 -0400 Received: from eggs.gnu.org ([208.118.235.92]:44383) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFMVW-0000KT-Iu for qemu-devel@nongnu.org; Tue, 12 Mar 2013 06:33:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UFMV5-0004mn-TZ for qemu-devel@nongnu.org; Tue, 12 Mar 2013 06:32:34 -0400 Received: from ozlabs.org ([2402:b800:7003:1:1::1]:34647) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFMV5-0004lr-6X; Tue, 12 Mar 2013 06:32:07 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 78A9B2C02BA; Tue, 12 Mar 2013 21:32:01 +1100 (EST) From: David Gibson To: agraf@suse.de Date: Tue, 12 Mar 2013 21:31:25 +1100 Message-Id: <1363084310-4115-24-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1363084310-4115-1-git-send-email-david@gibson.dropbear.id.au> References: <1363084310-4115-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2402:b800:7003:1:1::1 Cc: David Gibson , qemu-ppc@nongnu.org, afaerber@suse.de, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 23/48] mmu-hash32: Split direct store segment handling into a helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This further separates the unusual case handling of direct store segments from the main translation path by moving its logic into a helper function, with some tiny cleanups along the way. Signed-off-by: David Gibson --- target-ppc/mmu-hash32.c | 117 ++++++++++++++++++++++++----------------------- 1 file changed, 61 insertions(+), 56 deletions(-) diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 04ddf1d..dbde264 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -243,6 +243,62 @@ static int ppc_hash32_get_bat(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, return ret; } +static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, + target_ulong eaddr, int rwx, + hwaddr *raddr, int *prot) +{ + int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS)); + + LOG_MMU("direct store...\n"); + + if ((sr & 0x1FF00000) >> 20 == 0x07f) { + /* Memory-forced I/O controller interface access */ + /* If T=1 and BUID=x'07F', the 601 performs a memory access + * to SR[28-31] LA[4-31], bypassing all protection mechanisms. + */ + *raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF); + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return 0; + } + + if (rwx == 2) { + /* No code fetch is allowed in direct-store areas */ + return -4; + } + + switch (env->access_type) { + case ACCESS_INT: + /* Integer load/store : only access allowed */ + break; + case ACCESS_FLOAT: + /* Floating point load/store */ + return -4; + case ACCESS_RES: + /* lwarx, ldarx or srwcx. */ + return -4; + case ACCESS_CACHE: + /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */ + /* Should make the instruction do no-op. + * As it already do no-op, it's quite easy :-) + */ + *raddr = eaddr; + return 0; + case ACCESS_EXT: + /* eciwx or ecowx */ + return -4; + default: + qemu_log("ERROR: instruction should not need " + "address translation\n"); + return -4; + } + if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) { + *raddr = eaddr; + return 2; + } else { + return -2; + } +} + static int pte_check_hash32(struct mmu_ctx_hash32 *ctx, target_ulong pte0, target_ulong pte1, int h, int rwx) { @@ -404,66 +460,15 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, /* 3. Look up the Segment Register */ sr = env->sr[eaddr >> 28]; - pr = msr_pr; - ctx->key = (((sr & SR32_KP) && (pr != 0)) || - ((sr & SR32_KS) && (pr == 0))) ? 1 : 0; - /* 4. Handle direct store segments */ if (sr & SR32_T) { - LOG_MMU("direct store...\n"); - /* Direct-store segment : absolutely *BUGGY* for now */ - - /* Direct-store implies a 32-bit MMU. - * Check the Segment Register's bus unit ID (BUID). - */ - if ((sr & 0x1FF00000) >> 20 == 0x07f) { - /* Memory-forced I/O controller interface access */ - /* If T=1 and BUID=x'07F', the 601 performs a memory access - * to SR[28-31] LA[4-31], bypassing all protection mechanisms. - */ - ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF); - ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return 0; - } - - if (rwx == 2) { - /* No code fetch is allowed in direct-store areas */ - return -4; - } - - switch (env->access_type) { - case ACCESS_INT: - /* Integer load/store : only access allowed */ - break; - case ACCESS_FLOAT: - /* Floating point load/store */ - return -4; - case ACCESS_RES: - /* lwarx, ldarx or srwcx. */ - return -4; - case ACCESS_CACHE: - /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */ - /* Should make the instruction do no-op. - * As it already do no-op, it's quite easy :-) - */ - ctx->raddr = eaddr; - return 0; - case ACCESS_EXT: - /* eciwx or ecowx */ - return -4; - default: - qemu_log("ERROR: instruction should not need " - "address translation\n"); - return -4; - } - if ((rwx == 1 || ctx->key != 1) && (rwx == 0 || ctx->key != 0)) { - ctx->raddr = eaddr; - return 2; - } else { - return -2; - } + return ppc_hash32_direct_store(env, sr, eaddr, rwx, + &ctx->raddr, &ctx->prot); } + pr = msr_pr; + ctx->key = (((sr & SR32_KP) && (pr != 0)) || + ((sr & SR32_KS) && (pr == 0))) ? 1 : 0; ctx->nx = !!(sr & SR32_NX); vsid = sr & SR32_VSID; target_page_bits = TARGET_PAGE_BITS;