From patchwork Tue Mar 12 10:31:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 226923 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AB4922C02A3 for ; Tue, 12 Mar 2013 21:59:11 +1100 (EST) Received: from localhost ([::1]:42076 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFMXY-0002M5-SS for incoming@patchwork.ozlabs.org; Tue, 12 Mar 2013 06:34:40 -0400 Received: from eggs.gnu.org ([208.118.235.92]:44239) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFMVH-0000K2-AU for qemu-devel@nongnu.org; Tue, 12 Mar 2013 06:32:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UFMV3-0004kp-H1 for qemu-devel@nongnu.org; Tue, 12 Mar 2013 06:32:19 -0400 Received: from ozlabs.org ([203.10.76.45]:42971) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFMV2-0004jZ-Tf; Tue, 12 Mar 2013 06:32:05 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id E66742C02AB; Tue, 12 Mar 2013 21:32:00 +1100 (EST) From: David Gibson To: agraf@suse.de Date: Tue, 12 Mar 2013 21:31:13 +1100 Message-Id: <1363084310-4115-12-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1363084310-4115-1-git-send-email-david@gibson.dropbear.id.au> References: <1363084310-4115-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 203.10.76.45 Cc: David Gibson , qemu-ppc@nongnu.org, afaerber@suse.de, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 11/48] target-ppc: Disentangle hash mmu versions of cpu_get_phys_page_debug() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org cpu_get_phys_page_debug() is a trivial wrapper around get_physical_address(). But even the signature of get_physical_address() has some things we'd like to clean up on a per-mmu basis, so this patch moves the test on mmu model out to cpu_get_phys_page_debug(), moving the version for 64-bit hash MMUs out to mmu-hash64.c and the version for 32-bit hash MMUs to mmu-hash32.c Signed-off-by: David Gibson --- target-ppc/mmu-hash32.c | 17 +++++++++++++++-- target-ppc/mmu-hash32.h | 3 +-- target-ppc/mmu-hash64.c | 17 +++++++++++++++-- target-ppc/mmu-hash64.h | 3 +-- target-ppc/mmu_helper.c | 29 ++++++++++++++++------------- 5 files changed, 48 insertions(+), 21 deletions(-) diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 50f8c54..c0e5742 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -304,8 +304,9 @@ static int get_segment32(CPUPPCState *env, mmu_ctx_t *ctx, } -int ppc_hash32_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int access_type) +static int ppc_hash32_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, + target_ulong eaddr, int rw, + int access_type) { bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) || (access_type != ACCESS_CODE && msr_dr == 0); @@ -329,6 +330,18 @@ int ppc_hash32_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, } } +hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr) +{ + mmu_ctx_t ctx; + + if (unlikely(ppc_hash32_get_physical_address(env, &ctx, addr, 0, ACCESS_INT) + != 0)) { + return -1; + } + + return ctx.raddr & TARGET_PAGE_MASK; +} + int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx) { diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h index 8f1f2a9..8f10e0d 100644 --- a/target-ppc/mmu-hash32.h +++ b/target-ppc/mmu-hash32.h @@ -4,8 +4,7 @@ #ifndef CONFIG_USER_ONLY int pte32_is_valid(target_ulong pte0); -int ppc_hash32_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int access_type); +hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr); int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx); diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 32825ff..427b095 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -436,8 +436,9 @@ static int get_segment64(CPUPPCState *env, mmu_ctx_t *ctx, return ret; } -int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int access_type) +static int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, + target_ulong eaddr, int rw, + int access_type) { bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) || (access_type != ACCESS_CODE && msr_dr == 0); @@ -451,6 +452,18 @@ int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, } } +hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr) +{ + mmu_ctx_t ctx; + + if (unlikely(ppc_hash64_get_physical_address(env, &ctx, addr, 0, ACCESS_INT) + != 0)) { + return -1; + } + + return ctx.raddr & TARGET_PAGE_MASK; +} + int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx) { diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 3a53e61..665d3b0 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -6,8 +6,7 @@ #ifdef TARGET_PPC64 void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs); -int ppc_hash64_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, - target_ulong eaddr, int rw, int access_type); +hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr); int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx); #endif diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 287334f..818f1b5 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1310,11 +1310,6 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, #endif switch (env->mmu_model) { - case POWERPC_MMU_32B: - case POWERPC_MMU_601: - ret = ppc_hash32_get_physical_address(env, ctx, eaddr, rw, access_type); - break; - case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: if (real_mode) { @@ -1331,14 +1326,6 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, } break; -#if defined(TARGET_PPC64) - case POWERPC_MMU_64B: - case POWERPC_MMU_2_06: - case POWERPC_MMU_2_06d: - ret = ppc_hash64_get_physical_address(env, ctx, eaddr, rw, access_type); - break; -#endif - case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: if (real_mode) { @@ -1383,6 +1370,22 @@ hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr) { mmu_ctx_t ctx; + switch (env->mmu_model) { +#if defined(TARGET_PPC64) + case POWERPC_MMU_64B: + case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06d: + return ppc_hash64_get_phys_page_debug(env, addr); +#endif + + case POWERPC_MMU_32B: + case POWERPC_MMU_601: + return ppc_hash32_get_phys_page_debug(env, addr); + + default: + ; + } + if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) { return -1; }