From patchwork Tue Mar 12 09:23:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rojhalat Ibrahim X-Patchwork-Id: 226864 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id D27432C02C5 for ; Tue, 12 Mar 2013 20:24:14 +1100 (EST) Received: from mail-out.m-online.net (mail-out.m-online.net [IPv6:2001:a60:0:28:0:1:25:1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 793442C0293 for ; Tue, 12 Mar 2013 20:23:47 +1100 (EST) Received: from frontend1.mail.m-online.net (frontend1.mail.intern.m-online.net [192.168.8.180]) by mail-out.m-online.net (Postfix) with ESMTP id 3ZQ9ht0plMz3hhY2; Tue, 12 Mar 2013 10:23:25 +0100 (CET) Received: from mail.dmz.schenk (host-82-135-47-202.customer.m-online.net [82.135.47.202]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPS id 3ZQ9hs0dtGzbbtv; Tue, 12 Mar 2013 10:23:25 +0100 (CET) Received: from gwhaus.rt.schenk (gwhaus.rt.schenk [172.22.0.4]) by mail.dmz.schenk (Postfix) with SMTP id CEDE01C02FC; Tue, 12 Mar 2013 10:23:24 +0100 (CET) Received: from pcimr.localnet (pcimr.rt.schenk [172.22.10.20]) by gwhaus.rt.schenk (Postfix) with ESMTP id C5BA665329; Tue, 12 Mar 2013 10:23:24 +0100 (CET) From: Rojhalat Ibrahim To: Kumar Gala Subject: Re: [PATCH] Make PCIe hotplug work with Freescale PCIe controllers Date: Tue, 12 Mar 2013 10:23:24 +0100 Message-ID: <2399353.017i5G1tnZ@pcimr> User-Agent: KMail/4.9.5 (Linux/3.4.26; KDE/4.9.5; x86_64; ; ) In-Reply-To: <179EA411-594D-4774-903A-6C0445A01747@kernel.crashing.org> References: <3989200.gO920IVs04@pcimr> <179EA411-594D-4774-903A-6C0445A01747@kernel.crashing.org> MIME-Version: 1.0 Cc: linuxppc-dev@lists.ozlabs.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Monday 11 March 2013 12:17:42 Kumar Gala wrote: > > Rather than do it this way, we should do something like: > > fsl_indirect_read_config() { > link check > if (link) > indirect_read_config() > } > > and just add fsl_indirect_{r,w}_config into fsl_pci.c > > - k > Ok, how about this: Signed-off-by: Rojhalat Ibrahim --- arch/powerpc/sysdev/fsl_pci.c | 49 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 45 insertions(+), 4 deletions(-) #define MAX_PHYS_ADDR_BITS 40 @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) hose->first_busno = bus_range ? bus_range[0] : 0x0; hose->last_busno = bus_range ? bus_range[1] : 0xff; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, - PPC_INDIRECT_TYPE_BIG_ENDIAN); + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, + PPC_INDIRECT_TYPE_BIG_ENDIAN); if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { /* For PCIE read HEADER_TYPE to identify controler mode */ @@ -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev) if (ret) goto err0; } else { - setup_indirect_pci(hose, rsrc_cfg.start, - rsrc_cfg.start + 4, 0); + fsl_setup_indirect_pci(hose, rsrc_cfg.start, + rsrc_cfg.start + 4, 0); } printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 682084d..693db9f 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -36,6 +36,8 @@ static int fsl_pcie_bus_fixup, is_mpc83xx_pci; +static struct pci_ops *indirect_pci_ops; + static void quirk_fsl_pcie_header(struct pci_dev *dev) { u8 hdr_type; @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose) return 0; } +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) +{ + struct pci_controller *hose = pci_bus_to_host(bus); + + // check the link status + if ((bus->number == hose->first_busno) && (devfn == 0)) { + u32 ltssm = 0; + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm); + if (ltssm < PCIE_LTSSM_L0) { + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; + } else { + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; + } + } + return indirect_pci_ops->read(bus, devfn, offset, len, val); +} + +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val) +{ + return indirect_pci_ops->write(bus, devfn, offset, len, val); +} + +static struct pci_ops fsl_indirect_pci_ops = +{ + .read = fsl_indirect_read_config, + .write = fsl_indirect_write_config, +}; + +static void __init fsl_setup_indirect_pci(struct pci_controller* hose, + resource_size_t cfg_addr, + resource_size_t cfg_data, u32 flags) +{ + setup_indirect_pci(hose, cfg_addr, cfg_data, flags); + indirect_pci_ops = hose->ops; + hose->ops = &fsl_indirect_pci_ops; +} + #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)