From patchwork Tue Mar 12 06:43:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 226811 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CA1672C0291 for ; Tue, 12 Mar 2013 17:44:48 +1100 (EST) Received: from localhost ([::1]:37489 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFIx5-0007Vr-36 for incoming@patchwork.ozlabs.org; Tue, 12 Mar 2013 02:44:47 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFIwZ-0007QP-ER for qemu-devel@nongnu.org; Tue, 12 Mar 2013 02:44:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UFIwW-0006sv-8F for qemu-devel@nongnu.org; Tue, 12 Mar 2013 02:44:15 -0400 Received: from mail-ie0-x236.google.com ([2607:f8b0:4001:c03::236]:57225) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UFIwW-0006sm-2j for qemu-devel@nongnu.org; Tue, 12 Mar 2013 02:44:12 -0400 Received: by mail-ie0-f182.google.com with SMTP id k14so5888951iea.41 for ; Mon, 11 Mar 2013 23:44:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=c3mCTDTQLORPdxvlrewfk58ZoRlOIZ0jMQAJctLOTHU=; b=V5tzIfFEfjBzxfH0PtNkR0XPwTavliEZxIVjWnKizw4yZifhYTlr7AJury09vd3gUq nOy7C4QLFuloUG62ZPqcBf1qZ/4nSayDCabIcFlw11AilshuAclK5WAZvmYAJFqWx71v 2QwqMLnEF5bD9oompPRcP9HftU7sEGOL1nuk98qwhDiKtOSXohqSdlrJm9jTJvQF6vg7 yQnKod4WrKCRqFYD/HoxeO9P9rTaB2SzzBB+v2Z1LCMwK4TRAV/LhEtxpEl9nxN/5S3y uuwbZDfkwwufsjKMYiTn8GmnJDccBDfr6Jhw1PDioQ7XftKF2tBYdfj+bWAY1C5btvxv F1xw== X-Received: by 10.50.155.168 with SMTP id vx8mr10876898igb.73.1363070651518; Mon, 11 Mar 2013 23:44:11 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id wx2sm19571738igb.4.2013.03.11.23.44.08 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 11 Mar 2013 23:44:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 11 Mar 2013 23:43:43 -0700 Message-Id: <1363070631-21187-2-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1363070631-21187-1-git-send-email-rth@twiddle.net> References: <1363070631-21187-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4001:c03::236 Cc: jay.foad@gmail.com Subject: [Qemu-devel] [PATCH v2 1/9] tcg-arm: Use bic to implement and with constant X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This greatly improves the code we can produce for deposit without armv7 support. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 52 ++++++++++++++++++++++++++++++++++++++++++---------- tcg/arm/tcg-target.h | 2 -- 2 files changed, 42 insertions(+), 12 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 94c6ca4..9972792 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -145,6 +145,9 @@ static void patch_reloc(uint8_t *code_ptr, int type, } } +#define TCG_CT_CONST_ARM 0x100 +#define TCG_CT_CONST_INV 0x200 + /* parse target specific constraints */ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) { @@ -155,6 +158,9 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) case 'I': ct->ct |= TCG_CT_CONST_ARM; break; + case 'K': + ct->ct |= TCG_CT_CONST_INV; + break; case 'r': ct->ct |= TCG_CT_REG; @@ -275,16 +281,19 @@ static inline int check_fit_imm(uint32_t imm) * add, sub, eor...: ditto */ static inline int tcg_target_const_match(tcg_target_long val, - const TCGArgConstraint *arg_ct) + const TCGArgConstraint *arg_ct) { int ct; ct = arg_ct->ct; - if (ct & TCG_CT_CONST) + if (ct & TCG_CT_CONST) { return 1; - else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) + } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) { return 1; - else + } else if ((ct & TCG_CT_CONST_INV) && check_fit_imm(~val)) { + return 1; + } else { return 0; + } } enum arm_data_opc_e { @@ -482,6 +491,27 @@ static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst, } } +static void tcg_out_dat_rIK(TCGContext *s, int cond, int opc, int opinv, + TCGReg dst, TCGReg lhs, TCGArg rhs, + bool rhs_is_const) +{ + /* Emit either the reg,imm or reg,reg form of a data-processing insn. + * rhs must satisfy the "rIK" constraint. + */ + if (rhs_is_const) { + int rot = encode_imm(rhs); + if (rot < 0) { + rhs = ~rhs; + rot = encode_imm(rhs); + assert(rot >= 0); + opc = opinv; + } + tcg_out_dat_imm(s, cond, opc, dst, lhs, rotl(rhs, rot) | (rot << 7)); + } else { + tcg_out_dat_reg(s, cond, opc, dst, lhs, rhs, SHIFT_IMM_LSL(0)); + } +} + static inline void tcg_out_mul32(TCGContext *s, int cond, int rd, int rs, int rm) { @@ -1610,11 +1640,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, c = ARITH_SUB; goto gen_arith; case INDEX_op_and_i32: - c = ARITH_AND; - goto gen_arith; + tcg_out_dat_rIK(s, COND_AL, ARITH_AND, ARITH_BIC, + args[0], args[1], args[2], const_args[2]); + break; case INDEX_op_andc_i32: - c = ARITH_BIC; - goto gen_arith; + tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, + args[0], args[1], args[2], const_args[2]); + break; case INDEX_op_or_i32: c = ARITH_ORR; goto gen_arith; @@ -1802,8 +1834,8 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, { INDEX_op_muls2_i32, { "r", "r", "r", "r" } }, - { INDEX_op_and_i32, { "r", "r", "rI" } }, - { INDEX_op_andc_i32, { "r", "r", "rI" } }, + { INDEX_op_and_i32, { "r", "r", "rIK" } }, + { INDEX_op_andc_i32, { "r", "r", "rIK" } }, { INDEX_op_or_i32, { "r", "r", "rI" } }, { INDEX_op_xor_i32, { "r", "r", "rI" } }, { INDEX_op_neg_i32, { "r", "r" } }, diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index b6eed1f..354dd8a 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -49,8 +49,6 @@ typedef enum { #define TCG_TARGET_NB_REGS 16 -#define TCG_CT_CONST_ARM 0x100 - /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R13 #define TCG_TARGET_STACK_ALIGN 8