From patchwork Sat Mar 9 18:11:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 226361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DED9B2C033D for ; Sun, 10 Mar 2013 05:14:41 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750816Ab3CISOZ (ORCPT ); Sat, 9 Mar 2013 13:14:25 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:5558 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751168Ab3CISNL (ORCPT ); Sat, 9 Mar 2013 13:13:11 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Sat, 09 Mar 2013 10:18:18 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Sat, 09 Mar 2013 10:13:09 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Sat, 09 Mar 2013 10:13:09 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Sat, 9 Mar 2013 10:13:08 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Sat, 09 Mar 2013 10:13:08 -0800 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r29ID1sd027049; Sat, 9 Mar 2013 10:13:07 -0800 (PST) From: Laxman Dewangan To: CC: , , , , Laxman Dewangan Subject: [PATCH V2 2/5] ARM: DT: tegra114: Add i2c controller DT entry Date: Sat, 9 Mar 2013 23:41:15 +0530 Message-ID: <1362852678-13421-3-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1362852678-13421-1-git-send-email-ldewangan@nvidia.com> References: <1362852678-13421-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org NVIDIA's Tegra114 has 5 i2c controllers. These controllers have additional feature/configurations to make it functional over Tegra30's i2c controller driver. Add DT entry for i2c controllers and make it compatible with "nvidia,tegra114-i2c". Signed-off-by: Laxman Dewangan --- Changes from V1: - None arch/arm/boot/dts/tegra114.dtsi | 55 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 55 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index b73b8a6..14afbc8 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -135,6 +135,61 @@ clocks = <&tegra_car 65>; }; + i2c@7000c000 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c000 0x100>; + interrupts = <0 38 0x04>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 12>; + clock-names = "div-clk"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c400 0x100>; + interrupts = <0 84 0x04>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 54>; + clock-names = "div-clk"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c500 0x100>; + interrupts = <0 92 0x04>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 67>; + clock-names = "div-clk"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000c700 0x100>; + interrupts = <0 120 0x04>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 103>; + clock-names = "div-clk"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra114-i2c"; + reg = <0x7000d000 0x100>; + interrupts = <0 53 0x04>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + clocks = <&tegra_car 47>; + clock-names = "div-clk"; + }; + sdhci@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>;